Schematics

FCC ID: X4Y604U1

Schematics

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FCCID_1982695

5 4 3 2 1 VDD1_8 Place these caps under the DDR2. 2 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 VREF 1 C12 U2A -10uF-Z-0805-Y5V-10V -10nF-K-0402-X7R-50V -10nF-K-0402-X7R-50V -10nF-K-0402-X7R-50V -10nF-K-0402-X7R-50V -10nF-K-0402-X7R-50V -10nF-K-0402-X7R-50V -10nF-K-0402-X7R-50V -10nF-K-0402-X7R-50V -10nF-K-0402-X7R-50V -10nF-K-0402-X7R-50V -BCM47186B0KFBG-15*15-351PIN-TFBGA BGA351_0.65mm -100nF-K-0402-X7R-16V D N21 B21 DDR2_DATA_0 D VREF DDR_DATA_0 A22 DDR2_DATA_1 DDR2_ADDR_0 M22 DDR_DATA_1 D21 DDR2_DATA_2 DDR2_ADDR_1 L22 DDR_ADDR_0 DDR_DATA_2 B22 DDR2_DATA_3 DDR2_ADDR_2 M21 DDR_ADDR_1 DDR_DATA_3 C21 DDR2_DATA_4 DDR2_ADDR_3 L21 DDR_ADDR_2 DDR_DATA_4 D22 DDR2_DATA_5 U1 DDR2_ADDR_4 T22 DDR_ADDR_3 DDR_DATA_5 A21 DDR2_DATA_6 W9751G6JB-25-BGA84-WINBOND DDR2_ADDR_5 R21 DDR_ADDR_4 DDR_DATA_6 C22 DDR2_DATA_7 M9 G1 G3 G7 G9 R1 C1 C3 C7 C9 A1 E1 A9 E9 J9 J1 BGA84_0.8mm DDR2_ADDR_6 T21 DDR_ADDR_5 DDR_DATA_7 AB19 DDR2_DATA_8 VREF DDR2_ADDR_7 U21 DDR_ADDR_6 DDR_DATA_8 Y22 DDR2_DATA_9 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDL VDD VDD VDD VDD VDD DDR2_ADDR_8 U22 DDR_ADDR_7 DDR_DATA_9 AA18 DDR2_DATA_10 DDR2_ADDR_9 W22 DDR_ADDR_8 DDR_DATA_10 AB21 DDR2_DATA_11 DDR2_ADDR_0 M8 J2 DDR2_ADDR_10 K21 DDR_ADDR_9 DDR_DATA_11 AA19 DDR2_DATA_12 DDR2_ADDR_1 M3 A0 VREF DDR2_ADDR_11 V21 DDR_ADDR_10 DDR_DATA_12 AB20 DDR2_DATA_13 DDR2_ADDR_2 M7 A1 DDR2_ADDR_12 R22 DDR_ADDR_11 DDR_DATA_13 AA20 DDR2_DATA_14 DDR2_ADDR_3 N2 A2 G8 DDR2_DATA_0 DDR2_ADDR_13 F21 DDR_ADDR_12 DDR_DATA_14 AB18 DDR2_DATA_15 DDR2_ADDR_4 N8 A3 DQ0 G2 DDR2_DATA_1 DDR2_ADDR_14 V22 DDR_ADDR_13 DDR_DATA_15 DDR2_ADDR_5 N3 A4 A5 1Gb DQ1 DQ2 H7 DDR2_DATA_2 DDR_ADDR_14 DDR2_ADDR_6 N7 H3 DDR2_DATA_3 DDR2_BA_0 J21 DDR2_ADDR_7 P2 A6 A7 DDR2 SDRAM DQ3 DQ4 H1 DDR2_DATA_4 DDR2_BA_1 K22 DDR_BA_0 DDR_BA_1 VDD1_8 DDR2_ADDR_8 P8 H9 DDR2_DATA_5 DDR2_BA_2 J22 DDR2_ADDR_9 P3 A8 A9 32Mx16 DQ5 DQ6 F1 DDR2_DATA_6 DDR_BA_2 VDDMEM_G19 G19 DDR2_ADDR_10 M2 F9 DDR2_DATA_7 DDR2_DQM_0 G22 H19 DDR2_ADDR_11 P7 A10/AP A2,E2 DQ7 C8 DDR2_DATA_8 DDR2_DQM_1 AA22 DDR_DQM_0 VDDMEM_H19 L19 C DDR2_ADDR_12 R2 A11 DQ8 C2 DDR2_DATA_9 DDR_DQM_1 VDDMEM_L19 M19 C DDR2_ADDR_13 R8 A12 DQ9 D7 DDR2_DATA_10 DDR2_DQS_0 E22 VDDMEM_M19 N19 DDR2_ADDR_14 R3 A13/NC DQ10 D3 DDR2_DATA_11 DDR2_DQS_N_0 F22 DDR_DQS_0_P VDDMEM_N19 T19 R7 A14/NC DQ11 D1 DDR2_DATA_12 DDR_DQS_0_N VDDMEM_T19 U19 A15/NC DQ12 D9 DDR2_DATA_13 VDDMEM_U19 DDR2_BA_0 L2 DQ13 B1 DDR2_DATA_14 DDR2_DQS_1 Y21 VDD1_8 VDD1_8 DDR2_CLK DDR2_BA_1 L3 BA0 DQ14 B9 DDR2_DATA_15 DDR2_DQS_N_1 AA21 DDR_DQS_1_P DDR2_BA_2 L1 BA1 DQ15 DDR_DQS_1_N R2 R3 R1 BA2 DDR2_CKE P21 J8 B7 DDR2_DQS_1 DDR2_RAS_N H22 DDR_CKE 贴片电阻-100R-F-0402-1/16W CK_P UDQS_P DDR_RAS_N Place under the DDR2 K8 CK_N UDQS_N A8 DDR2_DQS_N_1 DDR2_CAS_N H21 DDR_CAS_N DDR2_WE_N G21 -30.9R-F-0402-1/16W -300R-F-0402-1/16W F7 DDR2_DQS_0 DDR2_ODT AB22 DDR_WE_N DDR2_CLK_N DDR2_CKE K2 LDQS_P E8 DDR2_DQS_N_0 DDR_ODT W18 NCOMP CKE LDQS_N DDR2_CLK P22 NCOMP W17 RCOMP B3 DDR2_DQM_1 DDR2_CLK_N N22 DDR_CLK RCOMP W16 PCOMP L8 UDM F3 DDR2_DQM_0 DDR_CLK_N PCOMP CS LDM R4 DDR2_RAS_N K7 K9 DDR2_ODT DDR2_CAS_N L7 RAS ODT DDR2_WE_N K3 CAS VDD1_8 -30.9R-F-0402-1/16W VSSDL WE VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSS VSS VSS VSS VSS B B R5 C13 A3 E3 J3 N1 P9 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 J7 VREF Place the VREF divider -1K-F-0402-1/16W -100nF-K-0402-X7R-16V close to the DDR2. R6 C14 VDD1_8 -1K-F-0402-1/16W -100nF-K-0402-X7R-16V 2 2 2 2 C32 C15 C16 C17 C18 C19 C20 1 1 1 1 -10uF-M-0603-X5R-6.3V -10nF-K-0402-X7R-50V -1nF-K-0402-X7R-50V -10nF-K-0402-X7R-50V -1nF-K-0402-X7R-50V -10nF-K-0402-X7R-50V -1nF-K-0402-X7R-50V A A Title Size Document Number Rev Place these caps under the 47186. B DDR2 1.0 Date: Wednesday, April 25, 2012 Sheet 5 of 18 5 4 3 2 1

5 4 3 2 1 VDD3_3 U2E -BCM47186B0KFBG-15*15-351PIN-TFBGA BGA351_0.65mm C21 U3 NFLSH_CLE Y1 P1 SFLASH_Q/NFLASH_CLE GPIO24/NFLASH_D0 P2 NFLSH_RDYBSY 5 8 NFLSH_RDYBSY V2 GPIO25/NFLASH_D1 R1 VDD3_3 NFLSH_RE_L 6 SI VCC SFLASH_D/NFLASH_RDYBSY0 GPIO26/NFLASH_D2 R2 SFLASH_CS_L 1 SCK 2 NFLSH_CLE -100nF-K-0402-X7R-16V NFLSH_RE_L V1 GPIO27/NFLASH_D3 T1 WP_L 3 CS# SO SFLASH_C/NFLASH_RE_L GPIO28/NFLASH_D4 T2 7 WP# 4 D SFLASH_CS_L W1 GPIO29/NFLASH_D5 U1 R7 HOLD#GND D SFLASH_CS_L GPIO30/NFLASH_D6 1 U2 -10K-J-0402-1/16W GPIO31/NFLASH_D7 IC-MX25L6406EM2I-12G-S08-MXIC Y2 NFLSH_ALE 11 NFLASH_ALE NFLSH_ALE 2 AA1 NFLSH_WE_L 11 NFLASH_WE_L NFLSH_WE_L W2 NFLASH_CE0_L C C VDD5 R9 C22 VDD3_3 -0R-J-0402-1/16W -100nF-K-0402-X7R-16V R11 R10 U19 5 MIC2025/ NI Place close to the USB connectors. SOT23-5 -0R-J-1206-1/4W FB1 4 IN 1 USB_5V_1 -10K-J-0402-1/16W 7 GPIO10_USB_EN EN OUT C23 3 FLG -100R-100M-0603-1.5A C24 C349 C25 U2C -100pF-J-0402-NPO-50V-walsin GND RREF -BCM47186B0KFBG-15*15-351PIN-TFBGA VDD3_3 BGA351_0.65mm 2 R12 R13 -22uF-Z-1206-Y5V-10V -22uF-Z-1206-Y5V-10V -100nF-K-0402-X7R-16V W6 AA10 C26 USB_AVDD3P3 USB_RREF 5 6 -4.02K-F-0402-1/16W Route these traces as a 90ohm differential pair. -0R-J-1206-1/4W SHIELD SHIELD USB_GND AA8 R14 USB_MONCDR AA9 -0R-J-0402-1/16W -100nF-K-0402-X7R-16V VDD2_5 USB_MONPLL B B AA7 W9 USB20H_CTL1_L 4 L1 3 4 C27 USB_AVDD2P5 AB9 USB_1_DP 3 GND USB20H_DP AB8 USB_1_DM 2 DP USB20H_DM 1 2 1 DM VBUS DLW21SN900HQ2L/NI D1 D2 VDD1_2 R15 USB -15.7*14.3*11.1mm-弯脚-A101 -100nF-K-0402-X7R-16V NI NI -0R-J-0402-1/16W J1 W7 C28 USB_AVDD1P2 U8 U9 USB_AGND_U8 AA6 USB_AGND_U9 VDD1_2 AB7 USB_AGND_AA6 -100nF-K-0402-X7R-16V USB_AGND_AB7 R16 USB_AVDD1P2PLL W8 C29 C30 USB_AVDD1P2PLL -1R-J-0402-1/16W -10uF-M-0603-X5R-6.3V -1nF-K-0402-X7R-50V VDD1_2 W5 AB6 14 HSIC_DVDD1P2 HSIC_DATA HSIC_DATA C31 U7 AB5 HSIC_DGND_U7 HSIC_STROBE HSIC_STROBE 14 AA5 AB4 HSIC_DGND_AA5 AA4 47186_HSIC_COMP HSIC_DGND_AB4 HSIC_COMP -100nF-K-0402-X7R-16V R17 1% NOTE: If both the USB port and HSIC port are not used in a design, Routing rules for the HSIC traces: -49.9R-F-0402-1/16W then make the following changes to the schematic: Route each of these traces on the top layer only - no vias! 1) Completely remove all the components connected to the USB and HSIC pins. Each is a 50ohm microstrip. A 2) Connect all the pins on the left side of the above symbol to GROUND. A Keep each trace at least 20mils away from any other copper on the top layer. 3) Leave all the pins on the right sided of the above symbol floating. Max trace length is 10cm (3.94 inches) maximum. Less than 5cm (1.97 inches) is best. Maximum capacitance to ground: 15pF Maximum skew between DATA and STROBE: 15ps = 100mils. Less than +/-50mils is best. NOTE: If the USB port is used but not the HSIC port, then make the following changes to the schematic: 1) Connect the HSIC_DVDD1P2 to 1.2V. 2) Connect the HSIC_DGND pins to GROUND. 3) Leave the HSIC_DATA, HSIC_STROBE, and HSIC_COMP pins floating. NOTE: If the USB port is not used but the HSIC port used, then make the following changes to the schematic: Title 1) Connect the USB power and ground pins as shown above. 2) Leave the USB_RREF, USB20H_CTL1, USB20H_DP, and USB20H_DM pins floating. Size Document Number Rev Custom Flash, USB, HSIC 1.0 Date: Wednesday, April 25, 2012 Sheet 6 of 18 5 4 3 2 1

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onton us m Aaycrncmen strap Pn runction setting Defallt porarity tsvorset vorcage used when 1P pore 15 in Foll mae: s s cntztepstt strapping opeion: oeeusv anlsy 1.2v 6 1M rewmyorsez vorcage used wien Fore 5 15 in RORIT woue: s s Set pore 5 pins as LtD signais. For 53125 only. 19 aenlsy wos crese Tore 5 sigoat serecn: nom: 53125 has on apectute us suson ort 5 signals i=tED ouspute modmm Minit of 1.207 on msos Taaple tne expedded 8051 microconsrotters it!s 127 pins. [ anesownsnow isable, 1=tnable wous » winnienmeos sakoe utpis_rupo_EN TiF pore confiquzacion: i Eepo: Tos on ssost serapping opeion: equire special beader tor all trattic Dizable internai sos1. 1 orvard all trattic reommiey ire Edommmmiaso en smmon we tepronecizo) Teb woie cee dacasnsss dor secemnge) 10 10 Exo: Tos hnConaes m a in woom m suresvco rome on e ow sysrreopmon Syaten c1so sor same s sume tor 10 Eeps: Tos sauwer s ancsowninom 10: soome 1 anome xamosiom a s cxmcrooet Tncerrace mds zor unpore 5 u> m beps Tos wBlrso « a ommummsmiornn oo: rersz, ox: wtz, 10: ranz, cuz keps: tov o momperorsen ag ehdre: me—neoetiso) TiP Foce eas: oo: sontz onnt so m Faps mion srmmsntorse h i hok 10: raut imomt heov: hion comEevronSm or Enable EEFRON mncersace i hepe: Tow i mav I—lig— w rome on 1: Enable SPL & MG/IDIO Intertace wf—voner mrissmr Tordvarding enabled as reses: m Eeps: Tos * Lzproort1:0) Strapping option: wl unsoomree WE O—Disabled (needs 5/¥ enable) see uepitoor 119 nabled (no 5/0 contiq needed) LEDMODETI] has incernal. pultup. suge arm i n m muser Tespy Eetistons senemren: o—bisabled i=tnabied Amovcaames novsameanee noimosseniee weuncamcaion 1\ suue vest pe toraams * Strapping option set at defaule with no option to change. bB wesr _Lhc@nzroy remmany t reomuaJBR use i m sut inour WorE: Route this comection with a remrtmremy Bsticen sepocate teace from the output fz cepecstors to the ¥Fo pin. bo 07 mrmpany t01‘ qbe 3 comect the YFD pin dizectly to the Yol2.E plane! samponen m evsee anesownanow $ 7 3 m ue moet m ree Strepping option: anesonzine Disable Energy Etticient Ethernet due to 53125 ervatas. im m sn ouser anesowzanow 1. esns w bu rmmovE(1:0)_Strapping option: vemener oarcoror—aite Whmenor oarcoror—se M BCGoname 7 see sienone = 000 = rortt wos ks wo iriessinnreson use sommmmonree Bfi cewone1 s w Bes us WH eneviaed Clommmince ht Cooees mm smm mouresorace ooo Em se m we is t—| t—| io o ovreoto—he— us me us m weoneus (Coonsnrsnane in uernuom sme sme wis o me uemow TeReH s hmbnate o from. ane smov ae s _c.mere. im ue mov w mew rerue is §B—A18 omoe an s m «24 uieher viciea sesommars rrese x § —we +8 a uxtontiun Mn ENIEETNE (1%_ in uon armrid ho hk wmeo uemee Moe r——£20—mn tho Heno Hewo scrom ieoonoorvosen sho wehoer wewe: es t inw08weenuner Heao wene Hon ueaneonoett Heaa HERGES es omiciren Heao Hene Herom . Heao ho nrme invomon wrhor weme: Pn ommc 500 1998sncouwer Eque Greantoce ce Fon (Efabnee wyouses mesouser rrue 1coserneceromo. Blen i pe e qo ismmobies Acfom % oimeoesso10 3 mmuuwer dithonen nrwe encmonsn Bok 3 rxmmwer ow ow Rowe catmorie k Efifiag2)Lg: > . oc mowes . is 3p mmmizer ducmertesos i ommeu nove: 1) Both the 53125 and the 47186 have built in series terminators for a Sookn output inpedance. A11 RGNIT teaces should have a 50—50ohm snpedance. ounnco 2) Te T% eaces, G_BD(G:0) and G_IICTRL, must be length masched to the G_THC Eoc tzace length to vitliin +/—100nils. Sane for RK traces relative to 6.RIC. . Mie dicee dree mite Gucies miter onner ce 5 o teo on ie omieose se rousouse. ensner ts iez© uen 53125 GioE Swich i —verammme mss : a

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Comections trom C223 to Rs6 6 Ro7 needs to be a "star—point?. Place the 0.iu® cops righe at tme 4szs pinc. veors weor un arssee weove Lo raze cone o vooues s HJGH viea am ol & tonsows mow — koE io i S #]0 3#]657 bew hss. Vioes es on an ve on 6i i es y y 3 $ *I T; %: *3 ; & $ $ $ wes nevunecommcance se conee vomes tonsows viaw & $ $ io f 3 H nnze.cormoners vnessraveoses veesisicens § $ ¢& $$ $& $$ $ $$ en s |Meramnitmnne &$ mf5 orssonmew i 5 $ & veer A _mase comvomm 5 —BMCSEEYOER—— nuse.cormvonees $ 5 i 3 $ $. OeE DARRiDiVates aresnoime —2 8 f A & $ $ 5 $ ie paseo vooith nnoconsevoorre & &8 & onsowninow Mektmenvooin Comectsons trom case enita e rios needs to be a "star—poid}?. Elace the 0.1uF cope righe at the §ozt pinc. wz gru00 n $ &e §$ veors 5 sys y L snmmwe o2 __snatnoores. s i B mes me $ $ &§ $$ & 5 onsswninow Es $——E bmmusmemene ordswnmen m sa corss are eaze cone 1 sooues onsoos mow onsomiew Hektmetvooiee $ £ e # # i=, & ¢$ $ 3$ 3$ 403£ wong .00 ii 5 so coret voours cssnu00 8$ $ 8 snmwcowsoree & $ 3 onsownmo T n & & memusn 4 ow ossonmew Corervoore $ onsowriew$. kess Piace the 10097 cans $ $ & right at pins 2s e on. § $ #48 C3 f & € 4; i & i & 3 & & $ $ : € xnurour H4lcx $ $ vers i$ verres i $ 2 & smexgac n 2 hvu m $i §$ om pr.io f 5 ° oi ow * ]MiEB 40— weorianrioout 4 4 s i A senome 2 soacunocrs a srusoes MMe meeise * * w i 1444 m an se rennes $& * ;& ;E 14#s arrp sour Yihrmiem seit rmmammemmnming 3 $$ *f55 as migfi@higpnns: 3 a $ i & nevunecosnicans nomocemoscain novocmmons i 3 i § $ 3 *4 £ 1 $ 3 $ & > & 3 $ & & ¥ f f & 5 as23e straping $ munction setting betout & & £ i Ontion Pin raz uo onmsce i& i& 6 cones_wrmons Sersal. Plash 1O present [detouit] o m x i f i Sersal Piash present eaze.cons 18. meag2 osomrema.conto rase.cons a= h Bs * % ’ coreo_wrtos sersar riash type ts 5t Iticzo (defouis) 1+ Sersal Piash Type is Arsel on m i——= .20mrems.coner exzecones a s coneoweesmx 0 = mstt mode (houza sering) 1 bim 220 F® mode (defouis) o ro 16 mp—————24 ar.50.mrems.coner exse.cones # pmas i coreowerss 0 beckprane ae 95 (90.4) iite 1 ro » rsurersue &z 1 backplane as 120 (125) Itle (deteult) eaeromo § restmanesion emecrm B coreo_wrzotx 0 bo mot use OP for contiguzetion (seteing)) 0 ro orioansierutszo u.0 e 1 * use off for contipuzetion {actour) oresecuimevennianae wl e use mo eaner o0anaverries y ceiojma amanerruniteecpuc a uidns senopried useeu/ 90 01 oo Erom RMW, ARK held in reset boot Erom ROW (deteuit) on none basmoov tCsoceuce 10 reserves 11 = Reseaved 2 coon w se corechce H—BI—AT—HE———————————jporemmuse is coreaimsn ommc i n hmnn Coremnins { Shaae ca pemmimncso is * Strepping poing option oo set at the devfult with no option » to change. s corecanists is rereste restim 3 cone. wmse am w cenoo0pre conwimn o ooo aamm se pemetmncso in corm wire me so corm mmm oo worzs reep the sseseorato corecarcn a—GiSAm—IHe a amsoersion amesoonsnoum tzace as shore as possible. Corermmins l coreraurcnn oneyeoseainsro [3 eebzcorermicon 8 Y — corrowtsx strepping Option: se wsxc noue. coreoairsmt strepping option: Oprion t set $6(90.4) peckplane ctock. seummsmnnc wmeont sttostmn m use wo 1 ae ms veors anciom ow nesounrow corm im m so ane aesonnviow cures aitom o wase uo Grr0(7:61 Serepping Opesones smesoommoum Set to boot trom Rolt tt serial tiash s corso_atox Serapping Option: cons_atotX Serapping Opeion: present ond propeanned, 4328 will boot Set to 0T use Ot? o contiqurstion. Set serial. thasn nor rreseir. trom sersal. tlash. A stendard 4.7% patiup will mos he able to everpover the 8179708 Joad on page 14 so a nmuasotas strong external pullup is needed to sssure a "i" s read for the strepping option vhen "Boot trom ROM® i2 se. m m bamannse * © 48236 Xtal, Analog, RF ® x Wermiy nemore m


Document Created: 2013-06-04 17:18:12
Document Modified: 2013-06-04 17:18:12
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