User Manual

FCC ID: WAP2005

Users Manual

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FCCID_2789803

PRELIMINARY CYBLE-222005-00 EZ-BLETM PRoC TM Module General Description The Cypress CYBLE-222005-00 is a fully certified and qualified Functional Capabilities module supporting Bluetooth Low Energy (BLE) wireless communication. The CYBLE-222005-00 is a turnkey solution n Up to 15 capacitive sensors for buttons or sliders with and includes onboard crystal oscillators, chip antenna, passive best-in-class signal-to-noise ration (SNR) and liquid tolerance components, and Cypress PRoC™ BLE. n 12-bit, 1-Msps SAR ADC with internal reference, The CYBLE-222005-00 supports a number of peripheral sample-and-hold (S/H), and channel sequencer functions (ADC, timers, counters, PWM) and serial n Two serial communication blocks (SCBs) supporting I2C communication protocols (I2C, UART, SPI) through its (master/slave), SPI (master/slave), or UART programmable architecture. The CYBLE-222005-00 includes a royalty-free BLE stack compatible with Bluetooth 4.1 and n Four dedicated 16-bit timer, counter, or PWM blocks provides up to 16 GPIOs in a small 10 × 10 × 1.80 mm package. (TCPWMs) The CYBLE-222005-00 is a complete solution and an ideal fit for n Programmable low voltage detect (LVD) from 1.8 V to 4.5 V applications requiring BLE wireless connectivity. n I2S master interface Module Description n Bluetooth Low Energy protocol stack supporting generic n Module size: 10.0 mm ×10.0 mm × 1.80 mm (with shield) access profile (GAP) Central, Peripheral, Observer, or Broadcaster roles n Drop-in compatible with CYBLE-022001-00 and includes additional VREF input n Switches between Central and Peripheral roles on-the-go n Bluetooth 4.1 single-mode module n Standard Bluetooth Low Energy profiles and services for interoperability n Industrial temperature range: –40 °C to +85 °C n Custom profile and service for specific use cases n 32-bit processor (0.9 DMIPS/MHz) with single-cycle 32-bit multiply, operating at up to 48 MHz Benefits n 256-KB flash memory The CYBLE-222005-00 module is provided as a turnkey n 32-KB SRAM memory solution, including all necessary hardware required to use BLE communication standards. n Watchdog timer with dedicated internal low-speed oscillator (ILO) n Proven, qualified, and certified hardware design ready to use n Two-pin SWD for programming n Small footprint (10 × 10 mm × 1.80 mm), perfect for space constrained applications n Up to 16 GPIOs configurable as open drain high/low, pull-up/pull-down, HI-Z analog, HI-Z digial, or strong output n Reprogrammable architecture n Certified to FCC, CE MIC, KC, and IC regulations n Fully certified module eliminates the time needed for design, development and certification processes n Bluetooth SIG 4.1 qualified n Bluetooth SIG qualified with QDID and Declaration ID Power Consumption n Flexible communication protocol support n TX output power: –18 dbm to +3 dbm n PSoC Creator™ provides an easy-to-use integrated design n Received signal strength indicator (RSSI) with 1-dB resolution environment (IDE) to configure, develop, program, and test a n TX current consumption of 15.6 mA (radio only, 0 dbm) BLE application n RX current consumption of 16.4 mA (radio only) n Low power mode support p Deep Sleep: 1.3 µA with watch crystal oscillator (WCO) on p Hibernate: 150 nA with SRAM retention p Stop: 60 nA with XRES wakeup Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-00214 Rev. ** Revised September 10, 2015

CYBLE-222005-00 Contents Overview............................................................................ 3 Regulatory Information .................................................. 25 Module Description...................................................... 3 FCC ........................................................................... 25 Pad Connection Interface ................................................ 5 Industry Canada (IC) Certification ............................. 26 Recommended Host PCB Layout ................................... 6 European R&TTE Declaration of Conformity ............ 26 Power Supply Connections and Recommended External MIC Japan ................................................................. 27 Components...................................................................... 9 KC Korea................................................................... 27 Connection Options..................................................... 9 Packaging........................................................................ 28 External Component Recommendation ...................... 9 Ordering Information...................................................... 30 Critical Components List ........................................... 11 Part Numbering Convention ...................................... 30 Antenna Design......................................................... 11 Document Conventions ............................................. 31 Electrical Specification .................................................. 12 Document History Page ................................................. 32 GPIO ......................................................................... 14 Sales, Solutions, and Legal Information ...................... 33 XRES......................................................................... 15 Worldwide Sales and Design Support....................... 33 Digital Peripherals ..................................................... 18 Products .................................................................... 33 Serial Communication ............................................... 20 PSoC® Solutions ...................................................... 33 Memory ..................................................................... 21 Cypress Developer Community................................. 33 System Resources .................................................... 21 Technical Support ..................................................... 33 Environmental Specifications ....................................... 24 Environmental Compliance ....................................... 24 RF Certification.......................................................... 24 Environmental Conditions ......................................... 24 ESD and EMI Protection ........................................... 24 Document Number: 002-00214 Rev. ** Page 2 of 33

CYBLE-222005-00 Overview Module Description The CYBLE-222005-00 module is a complete module designed to be soldered to the applications main board. Module Dimensions and Drawing Cypress reserves the right to select components (including the appropriate BLE device) from various vendors to achieve the BLE module functionality. Such selections will still guarantee that all height restrictions of the component area are maintained. Designs should be held within the physical dimensions shown in the mechanical drawings in Figure 1. All dimensions are in millimeters (mm). Table 1. Module Design Dimensions Dimension Item Specification Length (X) 10.00 ± 0.15 mm Module dimensions Width (Y) 10.00 ± 0.15 mm Length (X) 7.00 ± 0.15 mm Antenna location dimensions Width (Y) 5.00 ± 0.15 mm PCB thickness Height (H) 0.50 ± 0.10 mm Shield height Height (H) 1.10 ± 0.10 mm Maximum component height Height (H) 1.30 mm typical (chip antenna) Total module thickness (bottom of module to highest component) Height (H) 1.80 mm typical See Figure 1 on page 4 for the mechanical reference drawing for CYBLE-222005-00. Document Number: 002-00214 Rev. ** Page 3 of 33

CYBLE-222005-00 Figure 1. Module Mechanical Drawing Side View Top View Bottom View Note 1. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on recommended host PCB layout, see Figure 3 and Figure 4 on page 6. Document Number: 002-00214 Rev. ** Page 4 of 33

CYBLE-222005-00 Pad Connection Interface As shown in the bottom view of Figure 1 on page 4, the CYBLE-222005-00 connects to the host board via solder pads on the back of the module. Table 2 and Figure 2 detail the solder pad length, width, and pitch dimensions of the CYBLE-222005-00 module. Table 2. Solder Pad Connection Description Name Connections Connection Type Pad Length Dimension Pad Width Dimension Pad Pitch SP 22 Solder Pads 0.71 mm 0.41 mm 0.76 mm Figure 2. Solder Pad Dimensions Document Number: 002-00214 Rev. ** Page 5 of 33

CYBLE-222005-00 Recommended Host PCB Layout Figure 3 details the recommended PCB layout pattern for the host PCB. Dimensions are in mm. Figure 3. Recommended PCB Layout Pattern for CYBLE-222005-00 Top View (On Host PCB) To maximize RF performance, the host layout should follow these recommendations: 1. The ideal placement of the Cypress BLE module is in a corner of the host board with the chip antenna located at the far corner. This placement minimizes the additional recommended keep out area stated in item 2. 2. It is recommended that the area around the Cypress BLE module chip antenna should contain an additional keep out area, where no grounding or signal trace are contained. The keep out area applies to all layers of the host board. The recommended dimensions of the host PCB keep out area are shown in Figure 4 (dimensions are in mm). Figure 4. Recommended Host PCB Keep Out Area Around the CYBLE-222005-00 Chip Antenna Host PCB Keep Out Area Around Chip Antenna Document Number: 002-00214 Rev. ** Page 6 of 33

CYBLE-222005-00 Table 3 details the solder pad pitch (center-to-center) for each of the neighboring connections. Table 3. Module Solder Pad Connection Dimensions Pad X Pad Y Pad Pitch (Pad X - Pad Y) Comments Bottom Right Corner 1 1.64 mm Distance from bottom right corner to Pad 1 center 1 2 0.76 mm Distance from Pad 1 center to Pad 2 center 2 3 0.76 mm Distance from Pad 2 center to Pad 3 center 3 4 0.76 mm Distance from Pad 3 center to Pad 4 center 4 5 0.76 mm Distance from Pad 4 center to Pad 5 center 5 6 0.76 mm Distance from Pad 5 center to Pad 6 center Top Right Corner 7 0.81 mm Distance from top right corner to Pad 7 center 7 8 0.76 mm Distance from Pad 7 center to Pad 8 center 8 9 0.76 mm Distance from Pad 8 center to Pad 9 center 9 10 0.76 mm Distance from Pad 9 center to Pad 10 center 10 11 0.76 mm Distance from Pad 10 center to Pad 11 center 11 12 0.76 mm Distance from Pad 11 center to Pad 12 center 12 13 0.76 mm Distance from Pad 12 center to Pad 13 center 13 14 0.76 mm Distance from Pad 13 center to Pad 14 center 14 15 0.76 mm Distance from Pad 14 center to Pad 15 center 15 16 0.76 mm Distance from Pad 15 center to Pad 16 center 16 17 0.76 mm Distance from Pad 16 center to Pad 17 center 17 18 0.76 mm Distance from Pad 17 center to Pad 18 center Top Left Corner 19 1.50 mm Distance from top left corner to Pad 19 center 19 20 0.76 mm Distance from Pad 19 center to Pad 20 center 20 21 0.76 mm Distance from Pad 20 center to Pad 21 center 21 22 0.76 mm Distance from Pad 21 center to Pad 22 center Document Number: 002-00214 Rev. ** Page 7 of 33

CYBLE-222005-00 Table 4 details the solder pad connection definitions and available functions for each connection pad. Table 4 lists the solder pads on CYBLE-222005-00, the BLE device port-pin, and denotes whether the function shown is available for each solder pad. Each connection is configurable for a single option shown with a 3. Table 4. Solder Pad Connection Definitions Solder Pad Device UART SPI I2 C TCPWM[2] CapSense WCO ECO_OUT LCD SWD GPIO Number Port Pin Out [3] 1 GND Ground Connection 2 P4.1[4] 3(CTS) 3(MISO) 3 3(Sensor / 3 3 CTANK) 3 P5.1 3(TX) 3(SCLK) 3(SCL) 3 3(Sensor) 3 3 3 4 P5.0 3(RX) 3(SS) 3(SDA) 3 3(Sensor) 3 3 5 VDDR Radio Power Supply (1.9V to 5.5V) 6 VREF[5] Voltage Reference Input (Optional) 7 P1.6 3(RTS) 3(SS) 3 3(Sensor) 3 3 8 P0.7 3(CTS) 3(SCLK) 3 3(Sensor) 3 3(SWDCLK) 3 9 P0.4 3(RX) 3(MOSI) 3(SDA) 3 3(Sensor) 3 3 3 10 P0.5 3(TX) 3(MISO) 3(SCL) 3 3(Sensor) 3 3 11 GND Ground Connection 12 P0.6 3(RTS) 3(SS) 3 3(Sensor) 3 3(SWDIO) 3 13 P1.7 3(CTS) 3(SCLK) 3 3(Sensor) 3 3 14 VDD Digital Power Supply Input (1.71 to 5.5V) 15 XRES External Reset Hardware Connection Input 16 P3.5 3(TX) 3(SCL) 3 3(Sensor) 3 3 17 P3.4 3(RX) 3(SDA) 3 3(Sensor) 3 3 18 P3.7 3(CTS) 3(MISO) 3(Sensor) 3 3 3 19 P1.4 3(RX) 3(MOSI) 3(SDA) 3 3(Sensor) 3 3 20 P1.5 3(TX) 3(MISO) 3(SCL) 3 3(Sensor) 3 3 21 P3.6 3(RTS) 3 3(Sensor) 3 3 22 P4.0[6] 3(RTS) 3(MOSI) 3 3(CMOD) 3 3 Notes 2. TCPWM stands for timer, counter, and PWM. If supported, the pad can be configured to any of these peripheral functions. 3. The main board needs to connect both GND connections (Pad 1 and Pad 10) on the module to the common ground of the system. 4. When using the capacitive sensing functionality, Pad 2 (P4.1) can be connected to a CTANK capacitor (located off of Cypress BLE Module). CTank should be used if implementing a shield layer on the capacitive sensor. If used, this capacitor should be placed as close to the module as possible. 5. Analog block functionality is augmented for the user with the external VREF input. The internal bandgap may be bypassed with a 1-µF to 10-µF capacitor. 6. When using the capacitive sensing functionality, Pad 22 (P4.0) must be connected to a CMOD capacitor (located off of Cypress BLE Module). The value of this capacitor is 2.2 nF and should be placed as close to the module as possible. 7. If the I2S feature is used in the design, the I2S pins shall be dynamically routed to the appropriate available GPIO by PSoC Creator Document Number: 002-00214 Rev. ** Page 8 of 33

CYBLE-222005-00 Power Supply Connections and Recommended External Components Power Connections External Component Recommendation The CYBLE-222005-00 contains two power supply connections, In either connection scenario, it is recommended to place an VDD and VDDR. The VDD connection supplies power for both external ferrite bead between the supply and the module digital and analog device operation. The VDDR connection connection. The ferrite bead should be positioned as close as supplies power for the device radio. possible to the module pin connection. VDD accepts a supply range of 1.8 V to 5.5 V. VDDR accepts a Figure 5 details the recommended host schematic options for a supply range of 1.9 V to 5.5 V. These specifications can be found single supply scenario. The use of one or two ferrite beads will in Table 9. The maximum power supply ripple for both power depend on the specific application and configuration of the connections on the module is 100 mV, as shown in Table 7. CYBLE-222005-00. The power supply ramp rate of VDD must be equal to or greater Figure 6 details the recommended host schematic for an than that of VDDR. independent supply scenario. The recommended ferrite bead value is 330 Ω, 100 MHz. (Murata Connection Options BLM21PG331SN1D). Two connection options are available for any application: 1. Single supply: Connect VDD and VDDR to the same supply. 2. Independent supply: Power VDD and VDDR separately. Figure 5. Recommended Host Schematic Options for a Single Supply Option Single Ferrite Bead Option Two Ferrite Bead Option Figure 6. Recommended Host Schematic for an Independent Supply Option Document Number: 002-00214 Rev. ** Page 9 of 33

CYBLE-222005-00 The CYBLE-222005-00 schematic is shown in Figure 7. Figure 7. CYBLE-222005-00 Schematic Diagram Document Number: 002-00214 Rev. ** Page 10 of 33

CYBLE-222005-00 Critical Components List Table 5 details the critical components used in the CYBLE-222005-00 module. Table 5. Critical Component List Component Reference Designator Description Silicon U1 68-pin WLCSP Programmable Radio-on-Chip (PRoC) with BLE Crystal Y1 24.000 MHz, 10PF Crystal Y2 32.768 kHz, 12.5PF Antenna E1 2.4 – 2.5 GHz chip antenna Antenna Design Table 6 details the chip antenna used in the CYBLE-222005-00 module. The specifications listed are according to the vendor’s datasheet. The Cypress module performance improves many of these characteristics. For more information, see Table 8. Table 6. Chip Antenna Specifications Item Description Chip Antenna Manufacturer Johanson Technology Inc. Chip Antenna Part Number 2450AT18B100 Frequency Range 2400 – 2500 MHz Peak Gain 0.5 dBi typical Average Gain -0.5 dBi typical Return Loss 9.5 dB minimum Document Number: 002-00214 Rev. ** Page 11 of 33

CYBLE-222005-00 Electrical Specification Table 7 details the absolute maximum electrical characteristics for the Cypress BLE module. Table 7. CYBLE-222005-00 Absolute Maximum Ratings Parameter Description Min Typ Max Units Details/Conditions Analog, digital, or radio supply relative to VSS VDDD_ABS –0.5 – 6 V Absolute maximum (VSSD = VSSA) VCCD_ABS Direct digital core voltage input relative to VSSD –0.5 – 1.95 V Absolute maximum 3.0V supply Maximum power supply ripple for VDD and VDDR VDDD_RIPPLE – – 100 mV Ripple frequency of 100 kHz input voltage to 750 kHz VGPIO_ABS GPIO voltage –0.5 – VDD +0.5 V Absolute maximum IGPIO_ABS Maximum current per GPIO –25 – 25 mA Absolute maximum GPIO injection current: Maximum for VIH > VDD Absolute maximum current IGPIO_injection –0.5 – 0.5 mA and minimum for VIL < VSS injected per pin LU Pin current for latch up –200 200 mA – Table 8 details the RF characteristics for the Cypress BLE module. Table 8. CYBLE-222005-00 RF Performance Characteristics Parameter Description Min Typ Max Units Details/Conditions Configurable via register RFO RF output power on ANT –18 0 3 dBm settings Guaranteed by design RXS RF receive sensitivity on ANT – –91 – dBm simulation; High Gain Mode FR Module frequency range 2400 – 2480 MHz – GP Peak gain – 0.5 – dBi – GAvg Average gain – –0.5 – dBi – RL Return loss – –10.5 – dB – Table 9 through Table 47 list the module level electrical characteristics for the CYBLE-222005-00. All specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. Table 9. CYBLE-222005-00 DC Specifications Parameter Description Min Typ Max Units Details/Conditions VDD1 Power supply input voltage 1.8 – 5.5 V With regulator enabled Internally unregulated VDD2 Power supply input voltage unregulated 1.71 1.8 1.89 V supply VDDR1 Radio supply voltage (radio on) 1.9 – 5.5 V – VDDR2 Radio supply voltage (radio off) 1.71 – 5.5 V – Active Mode, VDD = 1.71 V to 5.5 V T = 25 °C, IDD3 Execute from flash; CPU at 3 MHz – 1.7 – mA VDD = 3.3 V IDD4 Execute from flash; CPU at 3 MHz – – – mA T = –40 °C to 85 °C T = 25 °C, IDD5 Execute from flash; CPU at 6 MHz – 2.5 – mA VDD = 3.3 V IDD6 Execute from flash; CPU at 6 MHz – – – mA T = –40 °C to 85 °C T = 25 °C, IDD7 Execute from flash; CPU at 12 MHz – 4 – mA VDD = 3.3 V Document Number: 002-00214 Rev. ** Page 12 of 33

CYBLE-222005-00 Table 9. CYBLE-222005-00 DC Specifications (continued) Parameter Description Min Typ Max Units Details/Conditions IDD8 Execute from flash; CPU at 12 MHz – – – mA T = –40 °C to 85 °C T = 25 °C, IDD9 Execute from flash; CPU at 24 MHz – 7.1 – mA VDD = 3.3 V IDD10 Execute from flash; CPU at 24 MHz – – – mA T = –40 °C to 85 °C T = 25 °C, IDD11 Execute from flash; CPU at 48 MHz – 13.4 – mA VDD = 3.3 V IDD12 Execute from flash; CPU at 48 MHz – – – mA T = –40 °C to 85 °C Sleep Mode, VDD = 1.8 to 5.5 V T = 25 °C, VDD = 3.3 V, IDD13 IMO on – – – mA SYSCLK = 3 MHz Sleep Mode, VDD and VDDR = 1.9 to 5.5 V T = 25 °C, VDD = 3.3 V, IDD14 ECO on – – – mA SYSCLK = 3 MHz Deep-Sleep Mode, VDD = 1.8 to 3.6 V T = 25 °C, IDD15 WDT with WCO on – 1.5 – µA VDD = 3.3 V IDD16 WDT with WCO on – – – µA T = –40 °C to 85 °C T = 25 °C, IDD17 WDT with WCO on – – – µA VDD = 5 V IDD18 WDT with WCO on – – – µA T = –40 °C to 85 °C Deep-Sleep Mode, VDD = 1.71 to 1.89 V (Regulator Bypassed) IDD19 WDT with WCO on – – – µA T = 25 °C IDD20 WDT with WCO on – – – µA T = –40 °C to 85 °C Hibernate Mode, VDD = 1.8 to 3.6 V T = 25 °C, IDD27 GPIO and reset active – 150 – nA VDD = 3.3 V IDD28 GPIO and reset active – – – nA T = –40 °C to 85 °C Hibernate Mode, VDD = 3.6 to 5.5 V T = 25 °C, IDD29 GPIO and reset active – – – nA VDD = 5 V IDD30 GPIO and reset active – – – nA T = –40 °C to 85 °C Stop Mode, VDD = 1.8 to 3.6 V T = 25 °C, IDD33 Stop-mode current (VDD) – 20 – nA VDD = 3.3 V T = 25 °C, IDD34 Stop-mode current (VDDR) – 40 –- nA VDDR = 3.3 V IDD35 Stop-mode current (VDD) – – – nA T = –40 °C to 85 °C T = –40 °C to 85 °C, IDD36 Stop-mode current (VDDR) – – – nA VDDR = 1.9 V to 3.6 V Stop Mode, VDD = 3.6 to 5.5 V T = 25 °C, IDD37 Stop-mode current (VDD) – – – nA VDD = 5 V T = 25 °C, IDD38 Stop-mode current (VDDR) – – – nA VDDR = 5 V IDD39 Stop-mode current (VDD) – – – nA T = –40 °C to 85 °C IDD40 Stop-mode current (VDDR) – – – nA T = –40 °C to 85 °C Document Number: 002-00214 Rev. ** Page 13 of 33

CYBLE-222005-00 Table 10. AC Specifications Parameter Description Min Typ Max Units Details/Conditions FCPU CPU frequency DC – 48 MHz 1.71 V ≤ VDD ≤ 5.5 V TSLEEP Wakeup from Sleep mode – 0 – µs Guaranteed by characterization 24-MHz IMO. Guaranteed by TDEEPSLEEP Wakeup from Deep-Sleep mode – – 25 µs characterization THIBERNATE Wakeup from Hibernate mode – – 2 ms Guaranteed by characterization TSTOP Wakeup from Stop mode – – 2 ms XRES wakeup GPIO Table 11. GPIO DC Specifications Parameter Description Min Typ Max Units Details/Conditions Input voltage HIGH threshold 0.7 × VDD – – V CMOS input VIH[8] LVTTL input, VDD < 2.7 V 0.7 × VDD – – V – LVTTL input, VDD >= 2.7 V 2.0 – – V – Input voltage LOW threshold – – 0.3 × VDD V CMOS input VIL LVTTL input, VDD < 2.7 V – – 0.3× VDD V – LVTTL input, VDD >= 2.7 V – – 0.8 V – Output voltage HIGH level VDD –0.6 – – V IOH = 4 mA at 3.3-V VDD VOH Output voltage HIGH level VDD –0.5 – – V IOH = 1 mA at 1.8-V VDD Output voltage LOW level – – 0.6 V IOL = 8 mA at 3.3-V VDD VOL Output voltage LOW level – – 0.6 V IOL = 4 mA at 1.8-V VDD Output voltage LOW level – – 0.4 V IOL = 3 mA at 3.3-V VDD RPULLUP Pull-up resistor 3.5 5.6 8.5 kΩ – RPULLDOWN Pull-down resistor 3.5 5.6 8.5 kΩ – IIL Input leakage current (absolute value) – – 2 nA 25 °C, VDD = 3.3 V IIL_CTBM Input leakage on CTBm input pins – – 4 nA – CIN Input capacitance – – 7 pF – VHYSTTL Input hysteresis LVTTL 25 40 – mV VDD > 2.7 V VHYSCMOS Input hysteresis CMOS 0.05 × VDD – – 1 – Current through protection diode to IDIODE – – 100 µA – VDD/VSS Maximum total source or sink chip ITOT_GPIO – – 200 mA – current Note 8. VIH must not exceed VDD + 0.2 V. Document Number: 002-00214 Rev. ** Page 14 of 33

CYBLE-222005-00 Table 12. GPIO AC Specifications Parameter Description Min Typ Max Units Details/Conditions TRISEF Rise time in Fast-Strong mode 2 – 12 ns 3.3-V VDDD, CLOAD = 25 pF TFALLF Fall time in Fast-Strong mode 2 – 12 ns 3.3-V VDDD, CLOAD = 25 pF TRISES Rise time in Slow-Strong mode 10 – 60 ns 3.3-V VDDD, CLOAD = 25 pF TFALLS Fall time in Slow-Strong mode 10 – 60 ns 3.3-V VDDD, CLOAD = 25 pF GPIO Fout; 3.3 V ≤ VDD ≤ 5.5 V 90/10%, 25 pF load, 60/40 duty FGPIOUT1 – – 33 MHz Fast-Strong mode cycle GPIO Fout; 1.7 V≤ VDD ≤ 3.3 V 90/10%, 25 pF load, 60/40 duty FGPIOUT2 – – 16.7 MHz Fast-Strong mode cycle GPIO Fout; 3.3 V ≤ VDD ≤ 5.5 V 90/10%, 25 pF load, 60/40 duty FGPIOUT3 – – 7 MHz Slow-Strong mode cycle GPIO Fout; 1.7 V ≤ VDD ≤ 3.3 V 90/10%, 25 pF load, 60/40 duty FGPIOUT4 – – 3.5 MHz Slow-Strong mode cycle GPIO input operating frequency FGPIOIN – – 48 MHz 90/10% VIO 1.71 V ≤ VDD ≤ 5.5 V Table 13. OVT GPIO DC Specifications (P5_0 and P5_1 Only) Parameter Description Min Typ Max Units Details/Conditions Input leakage (absolute value). IIL – – 10 µA 25°C, VDD = 0 V, VIH = 3.0 V VIH > VDD VOL Output voltage LOW level – – 0.4 V IOL = 20 mA, VDD > 2.9 V Table 14. OVT GPIO AC Specifications (P5_0 and P5_1 Only) Parameter Description Min Typ Max Units Details/Conditions TRISE_OVFS Output rise time in Fast-Strong mode 1.5 – 12 ns 25-pF load, 10%–90%, VDD=3.3 V TFALL_OVFS Output fall time in Fast-Strong mode 1.5 – 12 ns 25-pF load, 10%–90%, VDD=3.3 V 25 pF load, 10%-90%, TRISESS Output rise time in Slow-Strong mode 10 – 60 ns VDD = 3.3 V 25 pF load, 10%-90%, TFALLSS Output fall time in Slow-Strong mode 10 – 60 ns VDD = 3.3 V GPIO FOUT; 3.3 V ≤ VDD ≤ 5.5 V 90/10%, 25 pF load, 60/40 duty FGPIOUT1 – – 24 MHz Fast-Strong mode cycle GPIO FOUT; 1.71 V ≤ VDD ≤ 3.3 V 90/10%, 25 pF load, 60/40 duty FGPIOUT2 – – 16 MHz Fast-Strong mode cycle XRES Table 15. XRES DC Specifications Parameter Description Min Typ Max Units Details/Conditions VIH Input voltage HIGH threshold 0.7 × VDDD – – V CMOS input VIL Input voltage LOW threshold – – 0.3 × VDDD V CMOS input RPULLUP Pull-up resistor 3.5 5.6 8.5 kΩ – CIN Input capacitance – 3 – pF – VHYSXRES Input voltage hysteresis – 100 – mV – Current through protection diode to IDIODE – – 100 µA – VDD/VSS Document Number: 002-00214 Rev. ** Page 15 of 33

CYBLE-222005-00 Table 16. XRES AC Specifications Parameter Description Min Typ Max Units Details/Conditions TRESETWIDTH Reset pulse width 1 – – µs – SAR ADC Table 17. SAR ADC DC Specifications Parameter Description Min Typ Max Units Details/Conditions A_RES Resolution – – 12 bits A_CHNIS_S Number of channels - single-ended – – 8 8 full-speed A-CHNKS_D Number of channels - differential – – 4 Diff inputs use neighboring I/O A-MONO Monotonicity – – – Yes A_GAINERR Gain error – – ±0.1 % With external reference A_OFFSET Input offset voltage – – 2 mV Measured with 1-V VREF A_ISAR Current consumption – – 1 mA A_VINS Input voltage range - single-ended VSS – VDDA V A_VIND Input voltage range - differential VSS – VDDA V A_INRES Input resistance – – 2.2 kΩ A_INCAP Input capacitance – – 10 pF VREFSAR Trimmed internal reference to SAR –1 – 1 % Percentage of Vbg (1.024 V) Table 18. SAR ADC AC Specifications Details/ Parameter Description Min Typ Max Units Conditions A_PSRR Power-supply rejection ratio 70 – – dB Measured at 1-V reference A_CMRR Common-mode rejection ratio 66 – – dB A_SAMP Sample rate – – 1 Msps 806 Ksps for More Part Numbers devices Fsarintref SAR operating speed without external ref. – – 100 Ksps 12-bit resolution bypass A_SNR Signal-to-noise ratio (SNR) 65 – – dB FIN = 10 kHz A_BW Input bandwidth without aliasing – – A_SAMP/2 kHz A_INL Integral nonlinearity. VDD = 1.71 V to 5.5 V, –1.7 – 2 LSB VREF = 1 V to VDD 1 Msps A_INL Integral nonlinearity. VDDD = 1.71 V to 3.6 V, –1.5 – 1.7 LSB VREF = 1.71 V to VDD 1 Msps A_INL Integral nonlinearity. VDD = 1.71 V to 5.5 V, –1.5 – 1.7 LSB VREF = 1 V to VDD 500 Ksps A_dnl Differential nonlinearity. VDD = 1.71 V to –1 – 2.2 LSB VREF = 1 V to VDD 5.5 V, 1 Msps A_DNL Differential nonlinearity. VDD = 1.71 V to –1 – 2 LSB VREF = 1.71 V to VDD 3.6 V, 1 Msps A_DNL Differential nonlinearity. VDD = 1.71 V to –1 – 2.2 LSB VREF = 1 V to VDD 5.5 V, 500 Ksps Document Number: 002-00214 Rev. ** Page 16 of 33

CYBLE-222005-00 Table 18. SAR ADC AC Specifications (continued) Details/ Parameter Description Min Typ Max Units Conditions A_THD Total harmonic distortion – – –65 dB FIN = 10 kHz CSD CSD Block Specifications Details/ Parameter Description Min Typ Max Units Conditions VCSD Voltage range of operation 1.71 – 5.5 V IDAC1 DNL for 8-bit resolution –1 – 1 LSB IDAC1 INL for 8-bit resolution –3 – 3 LSB IDAC2 DNL for 7-bit resolution –1 – 1 LSB IDAC2 INL for 7-bit resolution –3 – 3 LSB SNR Ratio of counts of finger to noise 5 – – Ratio Capacitance range of 9 pF to 35 pF, 0.1-pF sensitivity. Radio is not operating during the scan IDAC1_CRT1 Output current of IDAC1 (8 bits) in High – 612 – µA range IDAC1_CRT2 Output current of IDAC1 (8 bits) in Low – 306 – µA range IDAC2_CRT1 Output current of IDAC2 (7 bits) in High – 305 – µA range IDAC2_CRT2 Output current of IDAC2 (7 bits) in Low – 153 – µA range Document Number: 002-00214 Rev. ** Page 17 of 33

CYBLE-222005-00 Digital Peripherals Timer Table 19. Timer DC Specifications Parameter Description Min Typ Max Units Details/Conditions ITIM1 Block current consumption at 3 MHz – – 42 µA 16-bit timer ITIM2 Block current consumption at 12 MHz – – 130 µA 16-bit timer ITIM3 Block current consumption at 48 MHz – – 535 µA 16-bit timer Table 20. Timer AC Specifications Parameter Description Min Typ Max Units Details/Conditions TTIMFREQ Operating frequency FCLK – 48 MHz TCAPWINT Capture pulse width (internal) 2 × TCLK – – ns TCAPWEXT Capture pulse width (external) 2 × TCLK – – ns TTIMRES Timer resolution TCLK – – ns TTENWIDINT Enable pulse width (internal) 2 × TCLK – – ns TTENWIDEXT Enable pulse width (external) 2 × TCLK – – ns TTIMRESWINT Reset pulse width (internal) 2 × TCLK – – ns TTIMRESEXT Reset pulse width (external) 2 × TCLK – – ns Counter Table 21. Counter DC Specifications Parameter Description Min Typ Max Units Details/Conditions ICTR1 Block current consumption at 3 MHz – – 42 µA 16-bit counter ICTR2 Block current consumption at 12 MHz – – 130 µA 16-bit counter ICTR3 Block current consumption at 48 MHz – – 535 µA 16-bit counter Table 22. Counter AC Specifications Parameter Description Min Typ Max Units Details/Conditions TCTRFREQ Operating frequency FCLK – 48 MHz TCTRPWINT Capture pulse width (internal) 2 × TCLK – – ns TCTRPWEXT Capture pulse width (external) 2 × TCLK – – ns TCTRES Counter Resolution TCLK – – ns TCENWIDINT Enable pulse width (internal) 2 × TCLK – – ns TCENWIDEXT Enable pulse width (external) 2 × TCLK – – ns TCTRRESWINT Reset pulse width (internal) 2 × TCLK – – ns TCTRRESWEXT Reset pulse width (external) 2 × TCLK – – ns Document Number: 002-00214 Rev. ** Page 18 of 33

CYBLE-222005-00 Pulse Width Modulation (PWM) Table 23. PWM DC Specifications Parameter Description Min Typ Max Units Details/Conditions IPWM1 Block current consumption at 3 MHz – – 42 µA 16-bit PWM IPWM2 Block current consumption at 12 MHz – – 130 µA 16-bit PWM IPWM3 Block current consumption at 48 MHz – – 535 µA 16-bit PWM Table 24. PWM AC Specifications Parameter Description Min Typ Max Units Details/Conditions TPWMFREQ Operating frequency FCLK – 48 MHz TPWMPWINT Pulse width (internal) 2 × TCLK – – ns TPWMEXT Pulse width (external) 2 × TCLK – – ns TPWMKILLINT Kill pulse width (internal) 2 × TCLK – – ns TPWMKILLEXT Kill pulse width (external) 2 × TCLK – – ns TPWMEINT Enable pulse width (internal) 2 × TCLK – – ns TPWMENEXT Enable pulse width (external) 2 × TCLK – – ns TPWMRESWINT Reset pulse width (internal) 2 × TCLK – – ns TPWMRESWEXT Reset pulse width (external) 2 × TCLK – – ns LCD Direct Drive Table 25. LCD Direct Drive DC Specifications Spec ID Parameter Description Min Typ Max Units Details/Conditions SID228 ILCDLOW Operating current in low-power mode – 17.5 – µA 16 × 4 small segment display at 50 Hz SID229 CLCDCAP LCD capacitance per segment/common – 500 5000 pF driver SID230 LCDOFFSET Long-term segment offset – 20 – mV SID231 ILCDOP1 LCD system operating current – 2 – mA 32 × 4 segments. VBIAS = 5 V 50 Hz at 25 °C SID232 ILCDOP2 LCD system operating current – 2 – mA 32 × 4 segments VBIAS = 3.3 V 50 Hz at 25 °C Table 26. LCD Direct Drive AC Specifications Spec ID Parameter Description Min Typ Max Units Details/Conditions SID233 FLCD LCD frame rate 10 50 150 Hz Document Number: 002-00214 Rev. ** Page 19 of 33

CYBLE-222005-00 Serial Communication Table 27. Fixed I2C DC Specifications Parameter Description Min Typ Max Units Details/Conditions II2C1 Block current consumption at 100 kHz – – 50 µA – II2C2 Block current consumption at 400 kHz – – 155 µA – II2C3 Block current consumption at 1 Mbps – – 390 µA – 2 1.4 II2C4 I C enabled in Deep-Sleep mode – – µA – Table 28. Fixed I2C AC Specifications Parameter Description Min Typ Max Units Details/Conditions FI2C1 Bit rate – – 400 kHz Table 29. Fixed UART DC Specifications Parameter Description Min Typ Max Units Details/Conditions IUART1 Block current consumption at 100 kbps – – 55 µA – IUART2 Block current consumption at 1000 kbps – – 312 µA – Table 30. Fixed UART AC Specifications Parameter Description Min Typ Max Units Details/Conditions FUART Bit rate – – 1 Mbps – Table 31. Fixed SPI DC Specifications Parameter Description Min Typ Max Units Details/Conditions ISPI1 Block current consumption at 1 Mbps – – 360 µA – ISPI2 Block current consumption at 4 Mbps – – 560 µA – ISPI3 Block current consumption at 8 Mbps – – 600 µA – Table 32. Fixed SPI AC Specifications Parameter Description Min Typ Max Units Details/Conditions FSPI SPI operating frequency (master; 6x over sampling) – – 8 MHz – Table 33. Fixed SPI Master Mode AC Specifications Parameter Description Min Typ Max Units Details/Conditions TDMO MOSI valid after SCLK driving edge – – 18 ns – MISO valid before SCLK capturing edge TDSI 20 – – ns Full clock, late MISO sampling Full clock, late MISO sampling used THMO Previous MOSI data hold time 0 – – ns Referred to Slave capturing edge Table 34. Fixed SPI Slave Mode AC Specifications Parameter Description Min Typ Max Units TDMI MOSI valid before SCLK capturing edge 40 – – ns TDSO MISO valid after SCLK driving edge – – 42 + 3 × TCPU ns MISO Valid after SCLK driving edge in TDSO_ext – – 50 ns external clock mode. VDD < 3.0 V THSO Previous MISO data hold time 0 – – ns TSSELSCK SSEL valid to first SCK valid edge 100 – – ns Document Number: 002-00214 Rev. ** Page 20 of 33

CYBLE-222005-00 Memory Table 35. Flash DC Specifications Parameter Description Min Typ Max Units Details/Conditions VPE Erase and program voltage 1.71 – 5.5 V – TWS48 Number of Wait states at 32–48 MHz 2 – – CPU execution from flash TWS32 Number of Wait states at 16–32 MHz 1 – – CPU execution from flash TWS16 Number of Wait states for 0–16 MHz 0 – – CPU execution from flash Table 36. Flash AC Specifications Parameter Description Min Typ Max Units Details/Conditions TROWWRITE[9] Row (block) write time (erase and program) – – 20 ms Row (block) = 128 bytes TROWERASE[9] Row erase time – – 13 ms – TROWPROGRAM[9] Row program time after erase – – 7 ms – TBULKERASE[9] Bulk erase time (128 KB) – – 35 ms – TDEVPROG[9] Total device program time – – 25 seconds – FEND Flash endurance 100 K – – cycles – FRET Flash retention. TA ≤ 55 °C, 100 K P/E cycles 20 – – years – FRET2 Flash retention. TA ≤ 85 °C, 10 K P/E cycles 10 – – years – System Resources Power-on-Reset (POR) Table 37. POR DC Specifications Parameter Description Min Typ Max Units Details/Conditions VRISEIPOR Rising trip voltage 0.80 – 1.45 V – VFALLIPOR Falling trip voltage 0.75 – 1.40 V – VIPORHYST Hysteresis 15 – 200 mV – Table 38. POR AC Specifications Parameter Description Min Typ Max Units Details/Conditions Precision power-on reset (PPOR) response TPPOR_TR – – 1 µs – time in Active and Sleep modes Table 39. Brown-Out Detect Parameter Description Min Typ Max Units Details/Conditions VFALLPPOR BOD trip voltage in Active and Sleep modes 1.64 – – V – VFALLDPSLP BOD trip voltage in Deep Sleep 1.4 – – V – Table 40. Hibernate Reset Parameter Description Min Typ Max Units Details/Conditions Note 9. It can take as much as 20 ms to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated. Document Number: 002-00214 Rev. ** Page 21 of 33

CYBLE-222005-00 Table 40. Hibernate Reset VHBRTRIP BOD trip voltage in Hibernate 1.1 – – V – Voltage Monitors (LVD) Table 41. Voltage Monitor DC Specifications Parameter Description Min Typ Max Units Details/Conditions VLVI1 LVI_A/D_SEL[3:0] = 0000b 1.71 1.75 1.79 V – VLVI2 LVI_A/D_SEL[3:0] = 0001b 1.76 1.80 1.85 V – VLVI3 LVI_A/D_SEL[3:0] = 0010b 1.85 1.90 1.95 V – VLVI4 LVI_A/D_SEL[3:0] = 0011b 1.95 2.00 2.05 V – VLVI5 LVI_A/D_SEL[3:0] = 0100b 2.05 2.10 2.15 V – VLVI6 LVI_A/D_SEL[3:0] = 0101b 2.15 2.20 2.26 V – VLVI7 LVI_A/D_SEL[3:0] = 0110b 2.24 2.30 2.36 V – VLVI8 LVI_A/D_SEL[3:0] = 0111b 2.34 2.40 2.46 V – VLVI9 LVI_A/D_SEL[3:0] = 1000b 2.44 2.50 2.56 V – VLVI10 LVI_A/D_SEL[3:0] = 1001b 2.54 2.60 2.67 V – VLVI11 LVI_A/D_SEL[3:0] = 1010b 2.63 2.70 2.77 V – VLVI12 LVI_A/D_SEL[3:0] = 1011b 2.73 2.80 2.87 V – VLVI13 LVI_A/D_SEL[3:0] = 1100b 2.83 2.90 2.97 V – VLVI14 LVI_A/D_SEL[3:0] = 1101b 2.93 3.00 3.08 V – VLVI15 LVI_A/D_SEL[3:0] = 1110b 3.12 3.20 3.28 V – VLVI16 LVI_A/D_SEL[3:0] = 1111b 4.39 4.50 4.61 V – LVI_IDD Block current – – 100 µA – Table 42. Voltage Monitor AC Specifications Parameter Description Min Typ Max Units Details/Conditions TMONTRIP Voltage monitor trip time – – 1 µs – SWD Interface Table 43. SWD Interface Specifications Parameter Description Min Typ Max Units Details/Conditions F_SWDCLK1 3.3 V ≤ VDD ≤ 5.5 V – – 14 MHz SWDCLK ≤ 1/3 CPU clock frequency F_SWDCLK2 1.71 V ≤ VDD ≤ 3.3 V – – 7 MHz SWDCLK ≤ 1/3 CPU clock frequency T_SWDI_SETUP T = 1/f SWDCLK 0.25 × T – – ns – T_SWDI_HOLD T = 1/f SWDCLK 0.25 × T – – ns – T_SWDO_VALID T = 1/f SWDCLK – – 0.5 × T ns – T_SWDO_HOLD T = 1/f SWDCLK 1 – – ns – Document Number: 002-00214 Rev. ** Page 22 of 33

CYBLE-222005-00 Internal Main Oscillator Table 44. IMO DC Specifications Parameter Description Min Typ Max Units Details/Conditions IIMO1 IMO operating current at 48 MHz – – 1000 µA – IIMO2 IMO operating current at 24 MHz – – 325 µA – IIMO3 IMO operating current at 12 MHz – – 225 µA – IIMO4 IMO operating current at 6 MHz – – 180 µA – IIMO5 IMO operating current at 3 MHz – – 150 µA – Table 45. IMO AC Specifications Parameter Description Min Typ Max Units Details/Conditions FIMOTOL3 Frequency variation from 3 to 48 MHz – – ±2 % With API-called calibration FIMOTOL3 IMO startup time – 12 – µs – Internal Low-Speed Oscillator Table 46. ILO DC Specifications Parameter Description Min Typ Max Units Details/Conditions IILO2 ILO operating current at 32 kHz – 0.3 1.05 µA – Table 47. ILO AC Specifications Parameter Description Min Typ Max Units Details/Conditions TSTARTILO1 ILO startup time – – 2 ms – FILOTRIM1 32-kHz trimmed frequency 15 32 50 kHz – Table 48. ECO Trim Value Specification Parameter Description Value Details/Conditions 24-MHz trim value Optimum trim value that needs to be loaded to register ECOTRIM 0x00003FFA (firmware configuration) CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_REG Document Number: 002-00214 Rev. ** Page 23 of 33

CYBLE-222005-00 Environmental Specifications Environmental Compliance This Cypress BLE module is built in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen Free (HF) directives. The Cypress module and components used to produce this module are RoHS and HF compliant. RF Certification The CYBLE-222005-00 module is certified under the following RF certification standards: n FCC n CE n IC n MIC n KC Environmental Conditions Table 49 describes the operating and storage conditions for the Cypress BLE module. Table 49. Environmental Conditions for CYBLE-222005-00 Description Minimum Specification Maximum Specification Operating temperature -40 °C 85 °C Operating humidity (relative, non-condensation) 5% 85% Thermal ramp rate – 3 °C/minute Storage temperature –40 °C 85 °C Storage temperature and humidity – 85 ° C at 85% ESD: Module integrated into system 15 kV Air – Components[10] 2.2 kV Contact ESD and EMI Protection Exposed components require special attention to ESD and electromagnetic interference (EMI). A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground. Device Handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability. Note 10. This does not apply to the RF pins (ANT, XTALI, and XTALO). RF pins (ANT, XTALI, and XTALO) are tested for 500-V HBM. Document Number: 002-00214 Rev. ** Page 24 of 33

CYBLE-222005-00 Regulatory Information FCC FCC NOTICE: The device CYBLE-222005-00, including the antenna 2450AT18B100 from Johanson Technology, complies with Part 15 of the FCC Rules. The device meets the requirements for modular transmitter approval as detailed in FCC public Notice DA00-1407.transmitter Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation. CAUTION: The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by Cypress Semiconductor may void the user's authority to operate the equipment. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions,ê may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: n Reorient or relocate the receiving antenna. n Increase the separation between the equipment and receiver. n Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. n Consult the dealer or an experienced radio/TV technician for help LABELING REQUIREMENTS: The Original Equipment Manufacturer (OEM) must ensure that FCC labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as well as the FCC Notice above. The FCC identifier is FCC ID: TBD. In any case the end product must be labeled exterior with "Contains FCC ID: TBD" ANTENNA WARNING: This device is tested with a standard SMA connector and with the antennas listed below. When integrated in the OEMs product, these fixed antennas require installation preventing end-users from replacing them with non-approved antennas. Any antenna not in the following table must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 for emissions. RF EXPOSURE: To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the approved antenna in the previous. The preceding statement must be included as a CAUTION statement in manuals, for products operating with the approved antennas in Table 6 on page 11, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removal instructions about the integrated radio module is not allowed. The radiated output power of CYBLE-222005-00 with the chip antenna mounted (FCC ID: TBD) is far below the FCC radio frequency exposure limits. Nevertheless, use CYBLE-222005-00 in such a manner that minimizes the potential for human contact during normal operation. End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with transmitter operating conditions for satisfying RF exposure compliance. Document Number: 002-00214 Rev. ** Page 25 of 33

CYBLE-222005-00 Industry Canada (IC) Certification CYBLE-222005-00 is licensed to meet the regulatory requirements of Industry Canada (IC), License: IC: TBD Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from www.ic.gc.ca. This device has been designed to operate with the antennas listed in Table 6 on page 11, having a maximum gain of 0.5 dBi. Antennas not included in this list or having a gain greater than 0.5 dBi are strictly prohibited for use with this device. The required antenna impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. IC NOTICE: The device CYBLE-222005-00 including the antenna 2450AT18B100 from Johanson technology, complies with Canada RSS-GEN Rules. The device meets the requirements for modular transmitter approval as detailed in RSS-GEN. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation. LABELING REQUIREMENTS: The Original Equipment Manufacturer (OEM) must ensure that IC labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product as well as the IC Notice above. The IC identifier is TBD. In any case, the end product must be labeled in its exterior with "Contains IC: TBD" European R&TTE Declaration of Conformity Hereby, Cypress Semiconductor declares that the Bluetooth module CYBLE-222005-00 complies with the essential requirements and other relevant provisions of Directive 1999/5/EC. As a result of the conformity assessment procedure described in Annex III of the Directive 1999/5/EC, the end-customer equipment should be labeled as follows: All versions of the CYBLE-222005-00 in the specified reference design can be used in the following countries: Austria, Belgium, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxem- bourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway. Document Number: 002-00214 Rev. ** Page 26 of 33

CYBLE-222005-00 MIC Japan CYBLE-222005-00 is certified as a module with type certification number TBD. End products that integrate CYBLE-222005-00 do not need additional MIC Japan certification for the end product. End product can display the certification label of the embedded module. KC Korea CYBLE-222005-00 is certified for use in Korea with certificate number TBD. Document Number: 002-00214 Rev. ** Page 27 of 33

CYBLE-222005-00 Packaging The CYBLE-222005-00 is offered in tape and reel pacakging. Figure 8 details the tape dimensions used for the CYBLE-222005-00. Figure 8. CYBLE-222005-00 Tape Dimensions Figure 9 details the orientation of the CYBLE-222005-00 in the tape as well as the direction for unreeling. Figure 9. Component Orientation in Tape and Unreeling Direction Document Number: 002-00214 Rev. ** Page 28 of 33

CYBLE-222005-00 Figure 10 details reel dimensions used for the CYBLE-222005-00. Figure 10. Reel Dimensions The CYBLE-222005-00 is designed to be used with pick-and-place equipment in an SMT manufacturing environment. The center-of-mass for the CYBLE-222005-00 is detailed in Figure 11. Figure 11. CYBLE-222005-00 Center of Mass Document Number: 002-00214 Rev. ** Page 29 of 33

CYBLE-222005-00 Ordering Information The CYBLE-222005-00 part number and features are listed in the following table. CPU Flash 12-Bit Part Number Speed Size CapSense SCB TCPWM SAR I2S LCD Package Packing (MHz) (KB) ADC CYBLE-222005-00 48 256 Yes 2 4 1 Msps Yes Yes 22-SMT Tape and Reel Part Numbering Convention The part numbers are of the form CYBLE-ABCDEF-GH where the fields are defined as follows. For additional information and a complete list of Cypress Semiconductor BLE products, contact your local Cypress sales representative. To locate the nearest Cypress office, visit our website. U.S. Cypress Headquarters Address 198 Champion Court, San Jose, CA 95134 U.S. Cypress Headquarter Contact Info (408) 943-2600 Cypress website address http://www.cypress.com Document Number: 002-00214 Rev. ** Page 30 of 33

CYBLE-222005-00 Acronyms Acronym Description BLE Bluetooth Low Energy Bluetooth SIG Bluetooth Special Interest Group CE European Conformity CSA Canadian Standards Association EMI electromagnetic interference ESD electrostatic discharge FCC Federal Communications Commission GPIO general-purpose input/output IC Industry Canada IDE integrated design environment KC Korea Certification MIC Ministry of Internal Affairs and Communications (Japan) PCB printed circuit board RX receive QDID qualification design ID SMT surface-mount technology; a method for producing electronic circuitry in which the components are placed directly onto the surface of PCBs TCPWM timer, counter, pulse width modulator (PWM) TUV Germany: Technischer Überwachungs-Verein (Technical Inspection Association) TX transmit Document Conventions Units of Measure Symbol Unit of Measure °C degree Celsius kV kilovolt mA milliamperes mm millimeters mV millivolt µA microamperes µm micrometers MHz megahertz GHz gigahertz V volt Document Number: 002-00214 Rev. ** Page 31 of 33

CYBLE-222005-00 Document History Page Document Title: CYBLE-222005-00 Bluetooth® Low Energy (BLE) Module Document Number: 002-00214 Orig. of Submission Revision ECN Description of Change Change Date ** PRELIM- DSO 09/10/2015 Preliminary datasheet for CYBLE-222005-00 module. INARY Document Number: 002-00214 Rev. ** Page 32 of 33

CYBLE-222005-00 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products PSoC® Solutions Automotive cypress.com/go/automotive psoc.cypress.com/solutions Clocks & Buffers cypress.com/go/clocks PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Interface cypress.com/go/interface Cypress Developer Community Lighting & Power Control cypress.com/go/powerpsoc Community | Forums | Blogs | Video | Training Memory cypress.com/go/memory PSoC cypress.com/go/psoc Technical Support Touch Sensing cypress.com/go/touch cypress.com/go/support USB Controllers cypress.com/go/USB Wireless/RF cypress.com/go/wireless © Cypress Semiconductor Corporation, 2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 002-00214 Rev. ** Revised September 10, 2015 Page 33 of 33 All products and company names mentioned in this document may be the trademarks of their respective holders.


Document Created: 2015-09-10 07:57:11
Document Modified: 2015-09-10 07:57:11
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