Block diagram RF ccts

FCC ID: Q639601

Block Diagram

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FCCID_601725

Commercially confidential Subject: Talladega Short Burst Data Module System Specification Iridium and CCL Use Only 5 RF Chain Design Figure 2: Receiver and Transmitter Block Diagram, Analogue Sections TX_PA_VDD_MON +5V + External DC Supply _ C? 940 uF RG7 +3V 50 mOhm Regulator TX_PA_CTL +3.0V Vcontrol TX_PWR_CNTL PA Module (U13) +5.0V Vcc TX_OK Celeritek CSM20403 Output match Output Interstage Driver Temperature TX RF SAW 1 TX IF Filter Directional Coupler & Harmonic Stage Match Stage compensated Hitachi HWEJ901 TFS215A and low-pass filter Attenuator (FLT9) From modulator filter DACs in Digital MMIC MMIC attenuator (FLT8) 215.0 I Section -20dB MHz Transmitter IQ RF Amplfier Q TX RF SAW 2 TX IF Amplifier MGA-62563 LO Notch filter TX Mixer Hitachi HWEJ901 BFP540F (Q9) (U12) CMY210 (U16) Reflected (FLT7) TX IQ Modulator and Forward 600kHz Reconstruction VGA MAX2510 (U14) filters TX_LO 1401 - 1411 MHz TX_F_PDETECT DC VSWR trip Attenuator LMV7239 RF Power detector -11 dB (U32) VSWR_TRIP LTC5509 (U9) TX_R_PDETECT Tx IF LO Buffer DC TX_IF_LO MGA-62563 (U7) 214.4MHz Antenna Attenuator RF Power detector Connector -2 dB LTC5509 (U29) TX_PREKEY 2W, +33dBm T/R SWITCH HMC546 (SW1) Rx 2nd IF 214.4MHz RX_LO Downconverter 1401 - 1411 MHz MAX2309 (U10) 600 kHz differential amplifier LNA1 LT6203 600kHz anti-alias Rx RF SAW 1 LNA2 Rx RF SAW 2 RX IF SAW Filter IP BFP540F (U11) filter 800MHz Notch Hitachi HWEJ901 BFP540F Hitachi HWEJ901 TFS215A IN (Q6) Filter (FLT5) (Q3) (FLT4) (FLT6) Real only, 600kHz Receiver differential signal to , QP -f 0 +f base-band ADC Rx Mixer QN CMY210 (U8) RC Polyphase Filter 3 Wire serial interface RX_VGC RXM_SHDNB RXM_STBYB RX_IF_LO 428.8 MHz 5.1 Frequency Plan The block diagram for the RF and IF analogue sections of the transmit and receive architecture is shown in Figure 2.3 The receiver is a conventional dual conversion superhet with an RF input of 1616MHz to 1626.5MHz, a first IF of 215MHz and a low second IF of 600kHz. A real-only output is provided at the second IF frequency for analogue-to-digital conversion at a sample rate of 2.4 MHz. The image of the second mixing process is suppressed by means of a two-section polyphase filter. The ASIC performs a final frequency conversion to bring the signal to a quadrature pair at zero frequency. The transmit frequency plan is identical although the architecture is different. The DSP processor generates a pair of baseband quadrature components at a sample rate of 200 kHz. In digital hardware these are translated to an IF of 600 kHz at a sample rate of 2.4 MHz. The two quadrature components are converted to analogue signals in the DACs, filtered to remove alias components and translated in a single-side band mixer to an IF of 215 MHz. After filtering the signal is then mixed to the output frequency of 1616 to 1626.5 MHz. 3 The first spin on the Talladega PCB will use the H1b 8W PA, all subsequent spins will use the new lower power 2W PA. C7321-S-002 v1.6 Page 18 of 43 07 September 2005


Document Created: 2005-11-11 10:35:16
Document Modified: 2005-11-11 10:35:16
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