Block Diagram

FCC ID: PQN44548TX2G4

Block Diagram

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FCCID_2604447

                                     TX Unit




                                                                            2412~2470MHz
Power 1                                    SOC Unit

(AA*4=6V


                                                               2.4G RF

                                                              Transmit
            Power
                                                                 ter
           managem                   MCU
                                                              Clock 12MHz
             ent



Power 2

(USB=5V)




                     Charging Unit             Key/VR input




                           LIPO


                   2.4GHz Transceiver for BT16P380

1. Block Diagram




                                                     vss_base
                                                    vdd_base




                                                                                                   qud_n_90
                                                                                                   qud_90



                                                                                                               op_in+
                                                                                                               pd_out




                                                                                                                             op_out




                                                                                                                                      v_cap
                                                                                                                                      v_sw
                                                                                vos1
                                                                                vos2


                                                                                          rssi
                                           REG
 vdd_lna     REG
 vss_lna
                     LNA            0                Channel                   Limiting                                 OP
                                                                                                 Demodulator                                  CMP
                                        90            Filter                     AMP                                    +                     +

                                                                                                                                        Data_out
                                                                                RSSI

            T/R SW                           Frequency
                     SW_EN
                                             Synthesizer




      ant            PA                      Modulator               Data_in




                                                  REG
                                                                vss_vco
                                                                vco_tune
                                                                vdd_vco
                             Bat_vss_3.3




                                                                cp_out
                             Bat_vdd_3.3



Document Created: 2015-05-05 12:16:30
Document Modified: 2015-05-05 12:16:30

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