Block Diagram

FCC ID: KUTQS101

Block Diagram

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FCCID_819804

PROPRIETARY INFORMATION




                      _o               IC 9            IC 4
                 SW1 —4                MCU             RF IC


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                                                                      MODEL:QS—101
                                                                      CPL CAPITAL PROSPECT LTD

                                                                      MODEL : QS—101
                                                                      BLOCK DIAGRAM
                                                                      DATE :6 JUN, 2007
                                                                      PAGE : 1 OF 1


(& Cchincon                                                            SmarthF® CC1100
14 Circuit Description




                                                     ADC    |—| E>            [0        [      2e      [
                                                               §1—|—&)—a
                                                               A_             E         @4             u"j —e so (GDO1)
   RE_P sa—
                                                                        "ul             4.             Q (|—la s
                                 | o         |__|          FREQ         EI              %
   RFN                    |            50                  SYNTHf       Eoo
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                                                                                                       lap

                                                               L                       L LELE
              rc osc          Blas                  xosc         t                                 .
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                              RBlas     xosc_ai xosc_o2

                                 Figure 2: GFIOO Simplified Block Diagram


A simplified block diagram of GZIZOO is shown                                 frequency synthesizer includes a completely
in Figure 2.                                                                  on—chip LC VCO and a 90 degree phase
                                                                              shifter for generating the | and Q LO signals to
GBO1IIOO ifeatures a lJow—lF receiver. The                                    the down—conversion mixers in receive mode.
received RF signal is amplified by the low—
noise amplifier (LNA) and down—converted in                                   A crystal is to be connected to XOSC_Q1 and
quadrature (I and Q) to the intermediate                                      XOSC_Q2. The crystal oscillator generates the
frequency (IF). At IF, the 1/Q signals are                                    reference frequency for the synthesizer, as
digitised by the ADCs. Automatic gain control                                 well as clocks for the ADC and the digital part.
(AGC), fine channel filtering, demodulation                                   A 4—wire SPI serial interface is used for
bit/packet      synchronization             is       performed                configuration and data buffer access.
digitally.
                                                                              The digital baseband includes support for
The transmitter part of GZIIOO is based on                                    channel configuration, packet handling and
direct synthesis of the RF frequency. The                                     data buffering.

15 Application Circuit
Only a few external components are required                                   Balun and RF matching
for using the GZIIOA The recommended                                          C131, C121, L121 and L131 form a balun that
application circuit is shown in Figure 3. The
                                                                              converts the differential RF port on 2GRIIOOJ to a
external components are described in Table
                                                                              single—ended RF signal (C124 is also needed
14, and typical values are given in Table 15.
                                                                              for DC blocking). Together with an appropriate
Bias resistor                                                                 LC network, the balun components also
                                                                              transform the impedance to match a 500
The bias resistor R171 is used to set an
                                                                              antenna (or cable). Component values for the
accurate bias current.
                                                                              RF balun and LC network are easily found
                                                                              using      the   SmartRF®      Studio       software.
                                                                              Suggested values for 315MHz, 433MHz and
                                                                              868/915MHz are listed in Table 15.



Chipcon AS              SmartRF® CC1100 Preliminary Data Sheet (rev. 1.0) 2005—04—25                         Page 14 of 68



Document Created: 2007-07-06 16:34:37
Document Modified: 2007-07-06 16:34:37

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