Circuit Diagram

FCC ID: EUGDJ-V5T

Block Diagram

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FCCID_26159

CIRCUIT DESCRIPTION 1) | Receiver System The receiver system is a double superheterodyne system with a 21.7 MHz first IF and a 450 kHz second IF. 1. Front End The received signal at any frequency in the 130.00— to 173.995—MHz range is passed through thelow—pass filter (L2, L3, L11, €13, C14, C15 and C60) and tuning circuit (L16 and D15), and amplified by the RF amplifier (Q11). The signal from Q11 is then passed through the tuning circuit (L17, L18, L19 and varicaps D13, D14 and D16) and converted into 21.7 MHz by the mixer (Q9). The tuning circuit, which consists of L16, L17, varicaps D15 and D13, L18, L19, varicaps D14 and D16, is controlled by the tracking voltage form the CPU so that it is optimized for the reception frequency. The local signal from the VCO is passed through the buffer (Q13), and supplied to the source of the mixer (Q9). The radio uses the lower side of the superheterodyne system. 2. IF Circuit The mixer mixes the received signal with the local signal to obtain the sum of and difference between them. The crystal filter (XKF1, XF2) selects 21.7 MHz frequency from the results and eliminates the signals of the unwanted frequencies. The first IF amplifier (Q10) then amplifies the signal of the selected frequency. 3. Demodulator Circuit After the signal is amplified by the first IF amplifier (Q10), it is input to pin 16 of the demodulator IC (IC5). The second local signal of 21.25 MHz (shared with PLL IC reference oscillation), which is oscillated by the internal oscillation circuit in IC1 and crystal (X1), is input through pin 1 of IC5. Then, these two signals are mixed by the internal mixer in IC5 and the result is converted into the second IF signal with a frequency of 450 kHz. The second IF signal is output from pin 3 of ICS to the ceramic filter (FL1), where the unwanted frequency band of that signal is eliminated, and the resulting signal is sent back to the IC5 tHrough pins 5. The second IF signal input via pin 5 is demodulated by the internal limiter amplifier and quadrature detection circuit in IC5, and output as an audio signal through pin 10. _ 4. Audio Circuit The audio signal from pin 10 of IC5 is compensated to the audio frequency characteristics in the de—emphasis circuit (R104, R103, C122, C121) and amplified by the AF amplifier (Q26). The signal is then input to pin 2 of the electronic volume (IC4) for volume adjustment, and output from pin 1. The adjusted signal is sent to the audio power amplifier (IC3) through pin 2 to drive the speaker. 5. Squelch Circuit The signal except for the noise component in AF signal of IC5 is cut by the active filter inside IC. The noise component is amplified and rectified, then converted to the DC voltage to output from pin13 of IC5. The voltage is led to pin 2 of CPU and compared with the setting voltage. The squelch will open if the input voltage is lower than the setting voltage.

2) Transmitter System 1. . Modulator Circuit The audio signal is converted to an electric signal in either the internal or external microphone, and input to the microphone amplifier (IC7). IC7 consists of two operational amplifiers; one amplifier (pins 5, 6, and 7) is composed of pre—emphasis and IDC circuits and the other (pins 1, 2, and 3) is composed of a splatter filter. The maximum frequency deviation is obtained by VR202 and input to the cathode of the varicap of the VCO, to change the electric capacity in the oscillation circuit. This produces the frequency modulation. 2. Power Amplifier Circuit The transmitted signal is oscillated by the VCO, amplified by the pre—drive amplifier (Q4) and drive amplifier (Q3), and input to the final amplifier (Q2). The signal is then amplified by the final amplifier (Q2) and led to the antenna switch (D1) and low—pass filter (L5, L4, L3, L2, C16, C15, C14 and C13), where unwanted high harmonic waves are reduced as needed, and the resulting signal is supplied to the antenna. 3. APC Circuit Part of the transmission power from the low—pass filter is detected by D6, converted to DC, and then amplified by a differential amplifier. The output voltage controls the bias voltage from the source of Q2 and Q3 to maintain the transmission power constant. 3) PLL Synthesizer Circuit 1. PLL The dividing ratio is obtained by sending data from the CPU (IC9) to pin 2 and sending clock pulses to pin 3 of the PLL IC (IC1). The oscillated signal from the VCO is amplified by the buffer (Q5) and input to pin 6 of IC1. Each programmable divider in IC1 divides the frequency of the input signal by N according to the frequency data, to generate a comparison frequency of 5 or 6.25 kHz. 2. Reference Frequency Circuit The reference frequency appropriate for the channel steps is obtained by dividing the 21.25 MHz reference oscillation (X1) by 4250 or 3400, according to the data from the CPU (IC9). When the resulting frequency is 5 kHz, channel steps of 5, 10, 15, 20, 25, 30, and 50 kHz are used. When it is 6.25 kHz, the 12.5 kHz channel step is used. 3. Phase Comparator Circuit The PLL (IC1) uses the reference frequency, 5 or 6.25kHz. The phase comparator in the ICl compares the phase of the frequency from the VCO with that of the comparison frequency, 5 or 6.25kHz, which is obtained by the internal divider in IC1I. 4. PLL Loop Filter Circuit If a phase difference is found in the phase comparison between the reference frequency and VCO output frequency, the charge pump output (pin 8) of IC1 generates a pulse signal, which is converted to DC voltage by the PLL loop filter and input to the varicap of the VCO unit for oscillation frequency control. 5. VCO Cireuit A Colpitts oscillation circuit driven by Q1 directly oscillates the desired frequency. The frequency control voltage determined in the CPU (IC9) and

PLL circuit is input to the varicaps (D32 and D34). This change the oscillation frequency, which is amplified by the VCO buffer (Q5) and output from the VCO unit. 4) —CPU and Peripheral Circuits 1. LCD Display Circuit The CPU turns ON the LCD via segment and common terminals with 1/4 the duty and 1/4 the bias, at the frame frequency is 112.5Hz. 2. Display Lamp Circuit L When the LAMP key is pressed, "H" is output form pin 50 of CPU (IC9) to the bases of Q12. Q12 then turn ON and the LEDs (D12 and D17) light. 3. Reset and Backup When the power form the DC jack or external battery increases from Circuits 0 V to 2.5 or more, "H" level reset signal is output form the reset IC (IC11) to pin 33 of the CPU (IC9), causing the CPU to reset. The reset signal, however, waits at 100, and does not enter the CPU untilthe CPU clock (X2) has stabilized. 4. S(Signal) Meter Circuit The DC potential of pin 8 of IC5 is input to pin 1 of the CPU (IC9), converted from an analog to a digital signal, and displayed as the S—meter signal on the LCD. 5. DTMF Encoder The CPU (IC9) is equipped with an internal DTMF encoder. The DTMEF signal is output from pin 10, through R102 and R158 (for level adjust—ment), and then through the microphone amplifier (IC7), and is sent to the varicap of the VCO for modulation. At the same time, the monitor—ing tone passes through the AF circuit and is output form the speaker.6. CTCSS Encoder The CPU (IC9) is equipped with an internal tone encoder. The tone signal (67.0 to 250.3 Hz) is output form pin 9 of the CPU to the varicap D3 of the VCO for modulation. 6. Tone Encoder The CPU (IC9) is equipped with an internal tone encoder.The tone signal (67.0 to 250.3 Hz) is output from pin 9 of the CPU to the varicap of the VCO for modulation. 7. DCS Encoder The CPU (IC9) is equipped with an internal DCS code encoder. The code (023 to 754) is output from pin 9 of the CPU to the varicap (D3) of the PLL reference oscillator. When DCS is ON, DCS MUTE cireuit (Q15—0N, Q18—0N, Q16—0FF) works. The modulation activates in X1 side only. 8. CTCSS, DCS Decoder The voice band of the AF output signal from pin 10 of IC5 is cut by sharp active filter IC8 (VCVS) and amplified, then led to pin 4 of CPU. The input signal is compared with the programmed tone frequency code in the CPU. The squelch will open when they match. 9. Clock Shift In the unlikely event that CPU clock noise is present on a particular operating frequency programmed into the radio, you can shift the CPU clock frequency to avoid

the CPU clock—noise. The output signal from pin 31 of the CPU turns on Q30. Then the oscillation frequency of X2 will be shifted about 300 ppm.

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Document Created: 1999-03-04 14:30:55
Document Modified: 1999-03-04 14:30:55
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