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FCC ID: ALHTKR-820N-3

Operational Description

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FCCID_73059

FCC ID: ALHTKR—820N—3 KR—SZO 2.1033(c) ADJUSTMENT (9) ADJUSTMENT Test equipment required for alignment Test Equipment Major Specifications 1. Standard Signal Generator Frequency range ’74-0 0~512MHz (SSG) Modulation Frequency modulation and external modulation. Output 0.1uV to greater than 1mV 2. Power meter Input impedance 50 ohms Operation frequency ‘700 to 512MH2z or more. Measurement capability Vicinity of 5OW, 3. Deviation meter Frequency range yao ~S12MH2 Digital Volt Meter Measuring range 1~10V DC. Accuracy High input impedance for minimum cireuit loading. 5. Oscilioscope DC through 3OMHz. 6. High sensitivity Frequency range 10Hz to 6COMHz. frequency counter Frequency stability 0.2 ppm or less. 7. Ammeter 15A. AF Voit Meter Frequency range 50Hz to 10kHz. [AFVTVM) Voltage range 3mV to 3V. 9. Audio Generator (AG} Frequency range 50Hz to SkHz or more. Output 0 and 1V. a 10. Distortion meter Capabitity 3% or less at 1kHz. Input level 5OmV to 10Vrms. 11. Voltmeter Measuring range 10~1.5V DC or less. Input impedance 50 kohms/V or greater. 12. 4 ohm dummy load Approx. 4 ohm, SW. The set has been adjusted for the frequencies shown in the following table. When required, re—adjust them follow— SIGNALING ing the adjustment procedure to obtain the frequencies you Ax Tx want in actual operation. °4 ay (Hz) pat OT (Hz) pat 1 67 77 ; RX freq‘ {MHz] TX freq‘ {(MHz) 2 192.8 179.9 TKR—820 k 469.900° }— 464.900 3 023 754 TkeS2e|ral _#31900 430420 a |_sas e — TkeR2)lr3s| _§11.3900 £04.900 s 100 351 __] TkRR2P |ky| #29.900 2y ] 00 MIC connector front view . . Rectangular plug * The following test cables are recommended. {€09—1571—05) Crimp terminal {€23—0613—05) M se @ rttc @ ett To aG MiC @ MICG AF vTVM MICG 7 G me .~ a n/SW DUMMY © noox fi;fi m To GNO SP ——————I @ cur ED) AFVTVM { (—"—"_—— Distortion meters SP Test cable for Microphone input Test cable for Speaker output

TKR—820 ADJUSTMENT Adjustment location Adjustment points Top view SIGNALING UNIT (x52—3140—10) vm AVAR UNIT {x43—3040—10) FINAL UNIT {x45—3250—10) vB3 © © on OTP1 is vat var vat VRS VR| © u7 s Lfo 5: v; QJ G a L17 T C ce3 13 TX—RX UNIT (x57—3270.10) ke7—20 Connect CLJ l LJ LJ J Bottom view [ J FINAL UNIT (X45—3250—10} Regh ie‘ TX—RX UNIT (X57—3270—10)_Bottom view CJ LJ OJ Front panel view nnrmmmenmmne c—al voruiee soueicn ""* O i Z a, KENWOOD

ADJUSTMENT lignment Measurement Adjustment Item Condition 1:-:1- Unit |Terminal| Unit Part Method Specifications/R emarks equipment Setting 1) AC voltage for destination : 120V DVM DUMMY LOAD (PLZ§0—50) AF VTVM DC AM METEAR 21 Connect to the DC output {OUT terminal) and GNO of the AVR unit. (+) Test equip« [1) Function : 0.19 resistor ment set—up Meter : 60A, 6OV DC : ON Power : ON SWwi : OFF Voitage 1} Power switch : ON DVM Output [AVAR |VR1 Adjust the load 13.6V 1 0.4V setting for 10A. {Verity power indicator lights.) (2) Vary the load for 2A —— 10A |DVM 13,6V : 0.7V CC draw. AF VTVM Less than 3OmV AC. (Set to 10A after check.} 3) Power switch : OFF ; Protection |1} SW1 : ON DVM Output JAVAR |VR2 |O.2v o.2v 0. 4v. VR2 : MAX CW. Power switch : ON 2) SW1 : OFF Check 13.6V : 0.4V Setfing 11 Write in freq‘ designed with EEP AOM writer. [For freg‘ writing, set the power of TKA—820 to ON.) 2) Connect the power cable to aAc Power meter the rear panel. 3) Final unit VA1 : MAX CCwW. Coupter 4) TX—ARX unit VA1 : MAX CCW. Deviation VR3 : MAX CCW. .| meter 5) Power ) Power SW : ON AG AF VTVM Frea — counter TKR—820 RX PLL * DVM [TXARX TP1 TX—RX |22 4.0V AOJ, 20. 1v Lock Voltage TX PLL TX—AX [TP2 TX—RK 125 4.0V ADJ. #0. V Lock Voltage l

TKR—820 ADJUSTMENT Meesurement Adjustment Item Condition *®¢ equipment unit [Terminal| Unit Parts Method Specifications/ Remmarks 8. TCXO 1} PTT : OFF (RX) Power TX—RX TP4 TX—RX|23 f— 21.4MHz AOJ. |2 10082 Freq‘ ADJ. Note : TCXO is adjusted meter [Foil precisely at 25°C, If it is FAEQ‘ side) readjusted, the frequency counter stability is changed. Do not touch it normally. 9. Power ACJ. |1) PTT : ON Power Hgar TX ANT |Final |VRI1 MAX CW. 2W or more. [APC}) meter panel MIN 2W or less, Ammeter 26W ADJ. #1W 10, Transmit 1} PTT : ON Power Rear |TX ANT |TX—AX|26 FAEQ‘ ADJ. of TX. |#100Hz Freq‘ ADJ. — meter panel FREQ® counter {1, Tone 1} T tone freq‘ being written, {Power Rear |TX ANT |Signal— |VRA4 |£0.75kHz *100Hz deviation Deviation meter filter : meter panel ing ADJ. LPF : SkMz, HPF : OFF, [Deviation De—emphasis : OFF meter PTT : ON 12. Maximum |1} Connect AG to the MIC Power Rear TX ANT [TX—RX VAR2 22. 1KHz ADJ. *100H2 deviation terminal. meter panel {22.4kHz ADJ. AOJ. AG : 1kHz/SQOmV Deviation In use of signaling.) Deviation meter filter : meter Adjust one more LPF : 20kHz, HPF : 50Hz, than the other by De—enphasis : 75Qusec, switching between TX—RX unit VR1 : MAX CW, P and +P. PTT : ON 13. MIC 1} AG : 1kHz/§SmV Power Rear [TX ANT |TX—RX |VR1 #1,5 KKz AOJ. £100H2z sensitivity PTT : ON meter panel *1.95K Hz aO4. | ADJ. Deviation In use of signaling.) ' ° meter 14. DQT 1} Connect AG to the TX—RX Power TX—RX |VR3 Make the demodu— waveform (TP3) and enter a square meter lation waveform correction wave of1d@Hz, 2Vp—p. Ceviation nest. Deviation meter filter : OFF |meter PYT : ON Oscillo— scope 15, RX AF VTVM|Rear |EXT.SP {Front |AF 0.78V/49 (Noise} sensitivity an panel panel |VOL. AOJ. dummy load SsG TKR—820

R—820 ADJUSTMENT Measurement Adjustment Item Condition Tcn- Unit |Tecrainat! Unit Pars Method Specifications/Remarks equipment 1} SSG output : SSG Rear |EXT.SP |TX—RX]L7 Reduce noise level 500uV/—5348m AF VTVM |panet L9 using L7, L9 and MOD : OFF Distortion L10 L10, meter Decrease the SSG 4n output so that noise dummy level is always 20 to load 3008 lower than 0.45V Repeat 3 to 4 times. 2} SSG output : Li8 Adjust for maximum 500uV/—5308m AF output. MOD : 1kHz/3kHz DEV. 3) SSG output : L16 Adjust for maximum 0.32pV/—117d8m L17 SINAO, Front |AF 0.45V/40 AOU. panel |VOL. Check SINAD 1208 or more, 4) SSG output : Front |AF 4.0Vv/49 AOJ. 500uV/—53d8m Panel |VOL. Check S/N 4508 or more. Distortion : 5% or less. queich 1) SSG output : OFF SSG Rear |EXT.SP SQL index angle Rotate SQL VA to a point AF VTVM |panel 8:00 ~ 10:00 at which noise disappears. 4n dummy . load 2} SSG output : Oscillo— Squeich should open. 0.22V/—121d48m scope eset 1} Signaling unit SSG Signal— D7 : LED should light. ueich VRI to VRS : MAX CCW, ing — ‘ . SSG output : OFF vaAl MAX CW. D7 : LED should go out. 21 $SG output : Rotate VR1 CCW. 0.2@V/~121d8m to a point at which D7 lights. Agip 1) SSG output : DVM Signal— (TP2 Signal— |VR2 1.0v 20.1V ie ADJ. 1.584V/—10348m ing ing The set time can be continuously varied by VAR2, 0 ~ SV — 0 ~ Ssec. 2) SSG output : Power Rear |TX ANT Check TX LED should light. 5012V/—S30Bm meter panel [RX ANT AEPEAT LED should light. AEPEAT SW : ON SsG 3) SSG ouiput : OFF TX LED should go out about 1 see. later after turning SSG OrF. I 1] The set time can be DVM Signal— |TP1 Signal« |VA3 |Set it to the target continuously varied by VR3 ing ing time. 0 ~0.3V : OFF ~0.5V : 3Osec. ~ SV : ~ Smin. rater 11,§5G output : Power Rear (EXT.SP [Signal |VRAS |* },5RHz *100Hz 5014V/—5348m meter panel ing mion SSG Deviation meter

TKR—820 ADJUSTMENT Measurement Adjustment Item Condition Test Specifications/ Remarks Unit Terminal Parts ' Method equipment 1. Signaling 1} SSG output : Turn the SSG squelch output so that the SINAD sensitivity becomes 1008. 10% @——'\I\N—J- ExT 2) SSG MOD Sw : EXT. MOD f moo AG1 FREQ‘: 1kHz AG2 FREQ!® : QT tone freg‘. 3] AG1 : Power switch OFF. 49 dummy load AG2 ouiput : Adjust the output level of AG2 so that AF VTVM SSG deviation becomes 0.75kHz. Oscilloscope Distartion meter 4) AG1 : Power switch ON. Rear EXT,.SP Signal— ] Check Open. AG1 output : Adjust the panel ing output tevel of AG1 so that the SSG deviation becomes 3.75kHz. (i.e., QT tone frequency/ 0.75kHz deviation , +1kHz/3kHz deviation) MONITOR Sw : OFF 2. TAKE. Front TAKE: Check The TAKEOVER LED must OveR panel Oven light on, switch

FCC ID: ALHTKR—820N—3 COMPONENTS DESCRIPTION OF COMPONENTS VR UNIT (X43—3040—10) DISPLAY UNIT {(X64—3070—11} Ref. No. Parts No. Descriptions Ref. No. Parts No, Descriptions ar~3 28C2712(Y) DC amplifier 1C1 4PD75104GE ~JW Microprocessor o4 258968(Q) DC amplitier 102 BR93LL46 EEPROM 05, 6 2N5885 DC amplitier iC3 MS51943BML Precision reference 01 18201 Rectifier 104 ANT7ENOS | Voltage regulator 5V D3 S2svs820 ARectifier ics uPCass8C Audio amplifier D4 1S5181 Temperature compensate 1C6 uPCASSEC Active filter D5 RD7.5EB2 Voltage reference Q1, 2 DTC114EK DC switch 06 15§181 LTemperature compensate as 2SA11621Y) Digital switch eld DTC114EK DC switch as 25C3326(A) AF switch INAL UNIT (X45—3250—10) a7,8 otciiaek DC switch Ref, No. Parts No. Descriptions 01 B30—0855—05 LED (Red) 1C1 M57729H—01—P TX power amplifier D2 830.0856—05 LED (Green} ar 2503357 AF amplifier D3 830—0855—05 LED [Red) 2 2502954 RF amplifier D4 ~6 185184 Voltage clamp as 25B946(Q) DC amplifier D7, 8 158181 Current steering Q4 25C2712(Y) DC amplifier D9 181555 Current steering QS, 6 25C3326(A) DC amplifier ©10, 11 188181 Current steering D1 19V172 RF switch D12 185184 Current steering D2 188226 Voltage reference D13 188181 Current steering D3, 4 188101 RF detect D16 830.0857—05 LED (Vellow) Ds pSAGA1 Reverse polarity protection D17 830—0856—05 LED (Green) D18 830—0857—05 LEO (Yellow} D21 198272 Current steering GNALING UNIT (X$2—3140—10) Ref. No, Parts No, Description c MC7sLOSM Voltage regulator SV TX—RX UNIT (X57—3270—10) C2 M51943BML Reset system Ref. No. Parts No. Descriptions c3 BA4SSBF Data recovery, active filter 1C1 uPC1242H AF power ampiifier C4 BA4SSBF Active filter 1C2 MB3756 Voltage regulator CS BA45SBF Data recovery 1C3 NJM4S5BD AF amplifier 26,7 gaasser Active filter 1c4 Arganios Voltage requlatar TB 220C256@TESB EPROM a1, 2 25C2712(Y) Voltage shift to TCTAHCST3AF Data latch as 25C4093(R27) | RF amplifier 210 BR33LC4G EEPROM 04, 5 25K125 IF amplifier ud uPD7?8310 AGF Microprocessor a6 25K302(GR) IF amplifier 1 DTC144EK Level transiator 7 2$C2712(Y) Level translator 2 DTC144EK Inverter 08 DTC114EK Inverter 3~7 DTC144EK DC switch Q9, 10 25C3326(A) Audio mute switch 3 DTA114EK DC switch 11 DTC114EK | DC switeh ) 25C3326(A) Audio amplifier Q12, 13 DTC114EK Inverter 10 25J106(GA) Audio amplifier D1 | 15V128 TX VCO output mute .2 1SS184 Current steering D2 15V172 TX VCO output mute 1 HSMBBAS Voltage clamp D3 155226 Voltage clamp ~6 188184 Current steering D4 NDA487C1T Double balanced modulator 830—0838—05 LED (Red) OS ~9, 11 199184 Current steering

KR—820 DESCRIPTION OF COMPONENTS RX PLL : 21, TX PLL : 24 (X58—3120—10) MIC AMP : 27 (X59—3210—10) Ref. No, Parts No. Descriptions Ref. no. Parts no. Descriptions 1C1 MBSO4F Prescaler 1C1 NJM4580M Mic amplifier/Limitter 1C2 JLC1075F PLL system 1C2 NJM455BM Limitter a1 25C3829TS RF amplifier 1C3 NJM4S5BM Active filter a2z~s5 DTC114EK Inverter on 25C3326(A) Muting switch o1 02023.0(2) Level shifter IF : 28 (X59—3220—10) RX VCO : 22 (X58—3150—10) Ref. No. Parts No. Descriptions Ref. No. Parts No. Descriptions 1C1 MC3351 $p IF system oi 2sksoenY 5U Osciliator af 25C2712(Y) Noise amplifier 02, 3 29C3356 Buffer amplifier D1 DA204K Noise detector Q4 25C3099 Buffer amplifier D1 1SV166 Tuning BPF/VCA : 29 (X59—3230—10) Ref, No. Parts No, Descriptions TX VCO : 25 (X58—3460—10) (a NJM4SSBM Audio amplifier Ref. No. Parts No. Descriptions 1C2 NJM455BM Active filter a1 25K508 NV (K#2> Oscillator 1C3 MS222FP Electronic attenuator 2 25C3356 Buffer amplifier 1C4 NJMA4SSBM Active filter 03, 4 28C3356 RF amplifier D1 1SVv166 Tuning D2 1SV164 Modulator

FCC ID: ALHTKR—820N—3 2.1033(c)(10) CIRCUIT DESCRIPTION TKR—820 CIRCUIT DESCRIPTION The signal applied to 28 is mixed with a 20.945MHz sig— Transmitter Circuit nal at IC1 in Z8, which produces a 45§kHz 2nd IF signal. The The signal generated at the transmitter frequency syn— signal obtained at the 2nd mixer is filtered by a 45§kHz ce— thesizer is amplified by AF amplifier transistors (Q1 and Q2) ramic filter (CF1} and amplified by limiting amplifier stages in and amplifier module {IC1} to a level of 25W in the power 1€1. The recovered audio signal from the incoming signal is ampilifier unit, The signal is then routed to the antenna con— also obtained at IC1 by a quadrature type FMdetector. This nector after going through a harmonics filter. recovered audio signal is then sent to the audio amplifier The transmitter output is detected by D3, 4 and is con— circuit and to the noise actuated squelch circuit. verted to a DC form. The DC signal thus detected is level in the receiver audio amplifier section, the recovered au— adjusted by APC control (VR1) and is applied to the base of dio signal from 28 is first applied to a bandpass filter/voltage Q6. The base current of Q3 is varied according to the differ— controlled amplifier {BPE/VCA, 29) unit. At this BPFENCA ance from the comparison voltage at Q5, 6 so that the col— unit, the signal is amplified and sent to pin 9 of CN6 as the lector voltages of 02 and the 1C1 first stage are controlled to DET signal. The signal is returned to 29 by way of the Sig— maintain the transmitter output level constant. naling unit. 1C1 forms a lowpass filter and a highpass filter, in the event an abnormai temperature rise occurs, the and IC2 forms a bandpass filter and lowpass filter in 29. The temperature is sensed by a thermistor (TH1) and reduces frequency components below 300H2z and above 3000Hz are the output power to a safe level. attenuated in the above filter circuits. The harmonics filter is of a fifth order Butterworth type The filtered audio signal is then applied to an electronic lowpass filter having a minimum attenuation of more than volume control (IC3), where the audio signal level is con— 5508 at the second harmonics frequency with a passband trolled by a DC voltage sent from the front panel volume insertion loss of less than 0.5dB. With a characteristics of contral. The signal is then de—emphasized and sent to the the transmitter final power amplifier module, which has audio power amplifier circuit (IC1) after going through more than 300B of attenuation for the frequency at the sec— squelch switches (Q9 and Q10}. ond harmonics or higher, total attenuation of harmonics is The alert signal is also applied to IC1, when a specific more than 700B. signaling board, which requires an audible alert through the speaker, is installed. The signal, which is amplified by IC1, Teax unut FINAL UNIT >| drives either the internal speaker or the optional external ANT speaker and this selection is done through the accessory TX ¥CO af amP Prioaive FINALHvenio cer connector located on the Final unit. 2 ai az ic1 Las.00 ss 1x ~— Bvco ATT m _M T‘ ,_] 0s ba cs 8 Pus 1st Local os ym T8 1~21. 00e ar ~ ‘; from Commen cont — Th PLL cirouit PEF AMP ass —s DC AMP o« _=~——— 1scif amp LPF Fig. 1 Transmitter block diagram x1 20.048 + CERAMIC Mz ALTER Receiver Circuit An incoming RF signal from the antenna is fed into a bandpass filter (L7). Then eliminated RF signal pass a pro— tector (D3). The signal is then amplified by an RF amplifier (Q3) and filtered again by bandpass filters {L9 and L10). After amplifi— cation and filtering, the signal is applied to a double balanced SIGNALiNG un oisPtay unit (aa) modulator (DBM, D4) for mixing with the first local signal generated at the Rx frequency synthesizer. The heterodyning action of the first mixer produces a 21.4MH2 first intermediate frequency (1st [F), which is ap— Fig. 2 Receiver block diagram plied to a 6—pole monalithic crystal filter (MCF, XF1) after being amplified by a buffer amplifier (Q4 and Q5 connected in parailel). The signal out of the MCF is further amplified by a 1st IF ampiifier (Q6) and sent to the IF unit (28).

TKR—820 CIRCUIT DESCRIPTION Squelch Circuit The high frequency companent of the recovered audio squeich switch transistors Q9 and Q10 along with the in— signal is fed to a noise amplifier within IC1 of Z8 and it is verted signal of transmit/receive control signal. The squelch further amplified by an external noise amplifier (Q1). The switch controls the input signal to the audio amplifier to signal is then detected by a noise detector (D1} and applied mute or unmute the receive audio. to the squelch switch in IC1. This detected noise is also While the busy LED is being controlled only by the noise routed to the squelch control {VR3) through the Display unit squelch cireuit, the actual audio signal is controlled by the {C/4) for adjusting the noise squelch sensitivity. following signals and in order to unmute the audio, each sig— The busy information is sent from the above IC1 in the nal must be in the condition as specified. Oisplay unit in serial format to turn on or off the busy LED. SQL signal = Low The squeich switch output and the audio controi {(AC) signal RB line = High from the signaling board are combined at D8 and applied to T/R signal = High AC signal = Low TX.AX UNIT MCouLe uit 29 : BPFVCA H: SQ OPEN 1: Sa MUTE i to| oN stonaunc Fomem ut i _ _ ._ _ 2IB2LEY oisrcay uaut uht L w Fig. 3 Squeich circuit RX Frequency Synthesizer TX Frequency Synthesizer The RX frequency synthesizer consists of three major cir— The TX frequency synthesizer consists of three major cir— cuits. They are the temperature compensated crystal oscil— cuits. They are the modulator/voltage controlled crystal os— lator (TCXO, 73}, RX voltage controlled oscillator (RX VCO, cillator (VCXO, 28), TX voitage contralled oscillator (TX VCO, Z2) and RX phase locked loop unit {RX PLL, 21}. Z5) and TX phase locked loop unit (TX PLL, 24}. The TCXO is operating at 12.8MHz and its frequency sta— The audio signal from the microphone amplifier and the bility is maintained within £2.5ppm from ~30°C to +60°C. Signaling unit is applied to the TX VCO {Z5) and the VCXO This output signal is fed to the frequency synthesizer IC (Z26) operating at 12.8MHz to obtain an FM modulated sig— {IC2) in 21. At IC2, this signal is divided by 1024 to become nal. And its frequency stability is maintained within a 12.5kHz reference signal. £*2.5ppm from —30°C to +60°C. This output signal is fed to The output from the RX VCO operates at the frequency the frequency synthesizer IC {IC2) in 74. At IC2, this signal of the receiver first local signat and a portion of the signal is is divided by 1024 to become a 12.5kHz reference signal. fed to a dual modulus counter formed by IC1 and IC2 in 71. The output from the TX VCO operates at the frequency of 1C1 divides the incoming signal by 1/64 or 1/65 depending the transmit signal and a portion of the signal is fed to a dual on the control line status sent from IC2. The output of the modulus counter formed by 1C1 and IC2 in 74. 1C1 divides dual modulus counter is also a 12.5kHz and this signal is the incoming signal by 1/64 and 1/65 depending on the con— compared against the 12.5kHz reference signal in a phase trol line status sent from IC2. The output of the dual modu— comparator at IC2; The output signal from the phase com— lus counter is also a 12.5kHz and this signal is compared parator is then fed back to the RX VCO after going through a against the 12.5kHz reference signal in a phase comparator charge pump and a lowpass filter to maintain the RX VCO at IC2. The output signal from the phase comparatoris then frequency. fed back to the TX VCO after going through a charge pump If this RX frequency synthesizer phase locked loop be— and a lowpass filter to maintain the TX VCO frequency. comes UNLOCK, the unlock condition is detected by IC2 If this TX frequency synthesizer phase locked loop be— and it prevents the trangmitter frequency synthesizer from comes UNLOCK, the uniock condition is detected by IC2 sending a transmitter signal to following amplifier stages in and it prevents the transmitter frequency synthesizer from order to prevent an unauthorized transmission. sending a transmitter.

TKR—820 CIRCUIT DESCRIPTION Microphone Amplifier The audio signal originating at the microphone is applied The processed audio signal is sent to the modulator/volt— to a microghone amplifier unit (27} after going through a mi— age controlled crystal oscillatar (VCXQ, 26) and voitage con— crophone sensitivity control (VR1}. troiled oscillator (TX VCO, Z5) in the transmitter frequency The signal is amplified and voltage limited by 1C1 and IC2 synthesizer via 103. in 27, then applied to an active lowpass filter/pre—emphasis network {1C3). 2 cug 1 from contacy, >—9MA my { en o I 1 t g—u9 ic2 a 4 (4————4>—fHg——n e 4 { »——% vexo wozd 7 ro msesten|+—|—| use io Iy——_«—— was 126| i2880 1 garance cHafce rume | } sionatine : unit Fig. 4 PLL & Modulation circuit block diagram Reset Circuit . Upon initial power up, the line voitage gradually increases and this causes the reset system {IC3) to generate a reset pulse. This reset pulse is applied to the microprocessor {IC1) to insure the initialization of the circuit. Cpflice sa From ROM writer {KPT—20 or XPT—50) it€]> a an_oa Power ON AESET When KPT—20 or KPT—50 connected Fig. 5 Reset circuit block diagram

TKR—820 CIRCUIT DESCRIPTION AVR Circuit This power supply uses a tapped secondary transformer If the load is shorted, comparator Q1 is turned OFF and to maintain low voltage between the pass transistor collec— current proportional only to that in the initial turn—on circuit is tors and emitters (Q5 and Q6) for excellent efficiency. Con— output. When the output is shorted, the output current trol and operating voltages are rectified and supplied inde— drops to 1A. This circuit protects the pass transistors, trans— cendently for good ripple characteristics. former and full wave bridge rectifies from thermai damage Temperature compensation for the regulator Zener diode Changing between AC and DC is done with the DC D5 and error amplifier transistor Q4 is provided by silicon switch (D101) for the TKR—820A only. The output from the diodes D4 and D6. AVR unit and the DC input from the external power input At initial POWER—ON Q3 is ON to turn—down Q4 base terminals are changed automatically. voltage. This prevents a surge voltage from being output when no load is connected. As C5 charges, Q2 turns ON to shut O3 OFF. Q4 is thereafter fuily ON. AMRUNT______ , e<———<————~ _ TsAony i Ti 1 I ariage | Main fter | 14 | | rectitir |—8—+| capacitor wransistor [ +—— | os"_| | tm I TI IG 1 0c ouput II looseecessee~ — —4 amp. camp. Pa D 11. lX rmeymax. 1 5l 11 1 Full wave x fiter Amplifing E 1 4 I recitir nacace Referance D4 i 1 eirouit 14 I i os 64 | ‘ 114 { Temp. limg Comparater D10 i os 10 1 14 I 14 : Tumon pu ——) notg.att |+—1O°F—390C ba I c 14 I 1 d I i0 i 1 Power switch i 1 $91 fuse 1 Transtormer 1 1 Ti AC input 1 0C input O———41DG switch I1 rmey °;” 1 oio1 1 1 t 1 Fig. 6 AVR circuit block diagram

TKR—820 CIRCUIT DESCRIPTION EEPROM Programming + Encoder operation in the transmit mode, the PTT terminal of CN1 becomes Programming of data into the EEPROM (IC2) in the Dis— "LOW* and this information is inverted to "HIGH® by Q7 be— play unit is done by connecting the KPT—20 pro— fore being applied to IC11. Upon receipt of this PTT signal or grammer to the transceiver by cable provided with the KPT— when the programmed tone has been decoded at the time 20 or KPT—50. When the programmer is connected to CN1 of the REPEAT operation, IC11 starts the encode function. in the Display unit, this causes microprocessor IC1 to go into The encode signal is sent out from output ports, A/D 0 reset condition. In the reset condition, the output ports of through A/D 7, of IC11 in a binary format and is fed to a 1C1 becomes high impedance and are isolated from the data ladder network resistor (CP1) for Digital—to—Analog signal transfer lines. This permits data transfers between the pro— conversion. The output signal from CP1, which is either the grammer and the EEPROM. QT tone or the DQT code, is routed to the TONE terminal of CN1 after going through a level control for madulating the Signaling Unit transmit signal. + Decoder operation The receive audio signal from the receiver section is fed + Local/Repeater operation to the Signaling unit. A part of this signal is returned to the When the REPEAT switch on the front panel of the main receive audio amplifier circuit and fed to mute circuit after body is set to ON, the repeater operation is engaged, while going through an active high—pass filter, in which any fre— when this switch is set to OFF, the full—duplex transceiver quencies below 300Hz are removed. The mute circuit con— operation is engaged. trol a transfer audio signal by microprocessor. The other part of the audio signal is fed through a fifth—order active + Preset squelch operation low—pass filter, of which the cut—off frequency is set at The squelch circuit for the repeater operation which is 220Hz, to discriminate the QT and DQT signals from other independent from the main body consists of noise condi— audio signals. tioner IC6 (1/2}, waveform shaper Q1, microprocesser IC11 The QT tone obtained from the above filtered audio signal and squelch sensitivity adjuster VRI1. is applied to the microprocessor (IC11} as an analog signal The preset squelch level, the hangup timer time and the for tone detection after being amplified by IC4 (2/2). time—out timer time are compared in IC11 respectively with The DQT code is passed through a low—pass filter IC3 {2/ the voltages at pins 30, 29 and 28 set by VR1, VRZ and VR3 2), of which the cut—off frequency is 140Hz, and the circuit with the reference of the voltage at pin 31 of IC11 and are consists of C3 (1/2) and 1C§ (1/2}, where the DC drift com— thus subject to software control. ponent {low frequency) is removed from the signal. The sig— nal is then amplified by ICS (2/2)}. The amplified signal is TAKEOVER Switch applied to IC1 after waveform shaping by Q2. The TAKEOVER switch is used to isolate the remote con— I€11 sends an audio control signal (AC) to the AC termi— nal of CN1 through an inverter (Q4) according to the status tral. (The remote control is isolated when the TAKEOVER of the incoming signal. !f the incoming QT tone or DQT code switch is pressed.) c matches the data stored, the AC terminal of CN1 is forced to become "LOW" to unmute the receive audio circuit. +— Monitor circuit The RESET terminal of CN1 is connected to the MONl— TOR and MIC MONITOR circuits in the repeater. The RESET terminal signal level goes to "HiIGH* state, if either the MONITOR switch is on or the microphones MONITOR switch is on, causing pin 4 (RESET) of IC11 to become "HIGH*. in this condition, the AC terminal of CN1 is held "LOW", enabling only the noise actuated squelch opera— tion.


Document Created: 2001-05-09 11:17:11
Document Modified: 2001-05-09 11:17:11
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