Block Diagram

FCC ID: AJK8221287

Block Diagram

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FCCID_383692

1.1.1 Functional Block Diagram Antenna A1 RF Card A2 Digital/PS Frequency Transmitter Synthesizer DAC & System Maintenance ADC / Processor Processor LPF T/R Control lines Frequency Synthesizer Receiver I/O - ARINC, Power VOCODER Discretes Supply Rear Connector LED Card A3 Rear A4 LED Interconnect Interface

1.1.2 Interface Diagram 1 1 8 .0 2 3 A c tiv e N e x t F re q u e n c y 1 1 8 .0 6 5 U p lo a d P re se t a n d A n n u n c ia t io n s Next V DL3 Enh V o ic e D a ta A N TE N N A LS 429 V /D TO O P P O S I TE S I D E C MU /O MS H S 429 F O R A U TO TU N E P O R TB O MSPO R T C M U P O R TB L S TU N I N G B HS CMU C MU O U T OMSO U T LS 429 O MS CMU V HF -2 1 0 0 (O p tio na l) H S POR T A C MU PO R T A OMS POR T A LS 429 O MS V/D V/D O MSIN POR TA +2 8 V D C L S TU N I N G LS 429 AN ALO G AU D IO P TT MIC P O R TA / B S E L E C T A NA LOG D A TA K E Y /2 /2 A C A RS /2 D A TA A U D I O O U T (O p tio na l) /2 D A TA A U D I O I N A U D IO S Y S T E M

1.1.3 System Interconnect Diagram

A4 ASSEMBLY (FRONT PANEL) A3 ASSEMBLY Phone/ RS- S. Rear Connector LED's Mic 232 T. ARINC 429 & Discretes MIC_GND RF DEBUG FP_ SELF_ ANT_ LRU_ CONTR DATA_INPUT_L FP_ _PORT TEST PASS PASS _PASS KEYLINE _TX BZT DATA_INPUT_H AUDIO_OUT_L DEBUG ANT_ LRU_ CONTR Filter GND _PORT _RX FAIL FAIL _FAIL AUDIO_OUT_H +28VDC_ MIC_INPUT_H MAIN_ BUSS MIC_INPUT_L TXRX_RF IF_SIGNAL AGC_LEVEL D8PSK_MODE MODE_3_CO_SITE PRESEL_1 RECEIVER T/R RX_RF PRESEL_2 PRESEL_3 SWITCH PRESEL_4 SCOM_TRESH RX_LO FAST_AGC T/R_SWITCH DSP/IO/MAINTENANCE/VOCODER TX_KEY CLOCK DATA RX/TX RX_STROBE TX_STROBE SYN. REF_FREQ TX_RF RX_SYNTH_LOCK TX_SYNTH_LOCK TX_RF_ BIAS DRIVE CLAMP_ENABLE I_MOD Q_MOD Q_PHASE_ADJ I_PHASE_ADJ TRANS. PA_DRIVER_BIAS PA_FINAL_BIAS V-FWD CHASSIS V_REV GND Q_DET PA_TEMP GND +28VDC_ PWR_WARN POS_3.3VDC MAIN_ BUSS PS_FREQ CLAMP_ON_INT_F +28VDC_CLAMPED POS_8VDC POWER NEG_8VDC POS_15VDC SUPPLY & CLAMP A1 ASSEMBLY A2 ASSEMBLY KEY COAX VHF-2100 ASSEMBLY INTERFACE DIAGRAM RIBBON

1.1.4 Transmitter Block Diagram +20 dBm RF Input TO RCVR INPUT I-Q -30 dB BTZ LP MOD -40 dB cplr T/R Coupler FILTER I Q PA PHASE_I FWD/REV SENSORS PHASE_Q LO RF LO I-Q DEMOD RF FWD_PWR REV_PWR PHASE Q I ADJUST PA TEMP SENSOR Q_INPUT ERROR AMPS/ LOOP FILTERS PA TEMP I_INPUT

1.1.5 Receiver Block Diagram PS#1 PS#2 PS#3 PS#4 RF Input -20 dB (from T/R Switch) COUPLER FM BAND 2 Pole 2 Pole SIMULCOM REJECT Filter Filter ATTN RF AMP Simulcomm 28.900 MHz Control Crystal Filter MIX +16 kHz BW IF AMP 28.900 MHz Lo Input IF output 146-165 MHz 17 dBm min 2nd Harmonic Rej Simulcomm AGC Detector/ Control Loop Amp Simulcomm Control output RF AMP and AM Detector Integrator/ VHF BP and 10.5 KHz Comparator/ FILTER Filter Monostable Mode 3 Co-Site Detect

1.1.6 Transmit Synthesizer Block Diagram +20 dBm 118-137 MHz Phase/ Reference Loop Filter/ Regenerative Frequency VCO Divider LPF Divide by 2 detector 236-274 MHz Hi Isolation Amp Programmable divide by N Prescaler 23.1 MHz Output Enable TCXO (on A2 assy) Synthesizer Programming Data 1.1.6.1 Detail of Regenerative Frequency Divider L R LPF - image rejection IF Mixer Pwr Splitter BPF (Series LC) Amp

1.1.7 Receiver Synthesizer Block Diagram . Loop Filter/LPF +17 dBm Min 146.900-166.000 MHz Reference Phase/Frequency Divider Detector VCO Programmable Divide by N Reverse Isolation Counter Amplifier 23.1 MHz TCXO - on A2 Assembly Dual-Modulus Prescaler Synthesizer Programming Data 1.1.8 A2 DSP Circuit Card Block Diagram

23.1 MHz WD AD5322 RX Preselect Timer VHF IF A/D D/A I Mod 28.875 Multirate WD X2 MHz Converter Decimator/ Q Mod AD6640 Parallel- Sport0 Rx Sport1 Tx bandpass sample I_Phase_ADJ Serial AD8801 AD6620 Q_Phase_ADJ 8 output Level I Channel Tx Data Audio Out H D/A Translators Level TMS320VC5416 & Filters Data Audio Out L Translators AD5322 DSP SYSP Q Channel Tx Sport2 TX & Filters D/A EPLD RX Audio H Sport0 TX Glue Sport1 Rx Sport2 Rx RX Audio L A/D Bus Logic Spare WD Sport0 Rx Intel Mic Audio H 28F160C TMS320VC5416 Flash Mic Audio L DSP 1M x 16 Data Audio In H VOCODER ARINC-429 Sport0 Tx OMS RX Data Audio In L External MAX146A/D Q Det WD Eland x2 80C188C AGC level ARINC- MAINTP 429 OMS (VHF-920 RX/TX DSP +28 Vdc 32.0 reuse) External Discrete Inputs: MHz Serial 600 baud V_FWD PTT Data Key V_REF SDI 1 SDI 2 CDFS_1_select CFDS_2_select Port B/A Select ARINC-429 HS/LS Tx 1-8 RS-232 front panel Tx Timer Disable Voice/Data_Select ARINC-429 HS/LS Rx 1-16 Snoopy 2 Tx_Synth Clock and Data Frequency offset enable Discrete Inputs Data_load Rx_Synth Clock and Data Rx Synth Lock Shop_mode Squelch Disable Tx Synth Lock Mode 3 Detect Discrete Outputs External Discrete Outputs: Air-Ground Audio Mute Selftest



Document Created: 2003-12-22 15:33:48
Document Modified: 2003-12-22 15:33:48
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