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FSC‐BT630 Datasheet FSC‐BT630 Bluetooth low energy 4.2 and 5 Specifications Module Datasheet Version 1.0 Shenzhen Feasycom Technology Co.,Ltd ‐1‐ www.feasycom.com

FSC‐BT630 Datasheet Copyright © 2013‐2017 Feasycom Technology. All Rights Reserved. Feasycom Technology reserves the right to make corrections, modifications, and other changes to its products, documentation and services at anytime. Customers should obtain the newest relevant information before placing orders. To minimize customer product risks, customers should provide adequate design and operating safeguards. Without written permission from Feasycom Technology, reproduction, transfer, distribution or storage of part or all of the contents in this document in any form is prohibited. Revision History Version Data Notes 1.0 2017/10/14 Initial Version Devin Wan Contact Us Shenzhen Feasycom Technology Co.,LTD Contact: Onen Ouyang Email: onen.ouyang@feasycom.com Address: Room 2004,20th Floor,Huichao Technology Building,Jinhai Road, Xixiang ,Baoan District,Shenzhen,518100,China. Tel: 86‐755‐27924639 Shenzhen Feasycom Technology Co.,Ltd ‐2‐ www.feasycom.com

FSC‐BT630 Datasheet 1. INTRODUCTION Overview Type 2 near field communication (NFC‐A) tag with wakeup‐on‐field and touch‐to‐pair capabilities FSC‐BT630 is a wireless microcontroller (MCU) targeting Postage stamp sized form factor Bluetooth 4.2 and Bluetooth 5 low energy applications. Temperature sensor Digital microphone interface (PDM) Very low active RF and MCU current and low‐power Up to 3x SPI master/slave(Max) mode current consumption provide excellent battery Quadrature decoder (QDEC) lifetime and allow for operation on small coin cell Embedded Bluetooth stack profiles support: SPP/iAP, batteries and in energy‐harvesting applications. HID, GATT, ANCS etc 3x real‐time counter (RTC) FSC‐BT630 contains a 32‐bit ARM® Cortex®‐M4 core that OTA upgrade support runs at 64 MHz as the main processor and a rich MFI Support peripheral feature set that includes a unique ultra‐low Support External Antenna power sensor controller. This sensor controller is ideal for RoHS compliant interfacing external sensors and for collecting analog and digital data autonomously while the rest of the system is in sleep mode. Thus, FSC‐BT630 is great for a wide range Application of applications where long battery lifetime, small form Internet of Things (IoT) factor, and ease of use is important. • Home automation • Sensor networks It supports GAP, ATT/GATT, SMP, L2CAP profiles. It • Building automation integrates Baseband controller in a small package • Industrial (Integrated Ceramic antenna), so the designers can have • Retail better flexibilities for the product shapes. Personal area networks • Health/fitness sensor and monitor devices Features • Medical devices • Key fobs and wrist watches Support the Bluetooth 4.2 core specification and 5 Interactive entertainment devices Specifications • Remote controls Low power • Gaming controllers RSSI (1 dB resolution) Beacons •A4WP wireless chargers and devices UART programming and data interface (baudrate can •Remote control toys up to 921600bps) •Computer peripherals and I/O devices: I2S audio interface Mouse/Keyboard/Multi‐touch track pad/Gaming I2C/AIO/PIO/PWM control interfaces Shenzhen Feasycom Technology Co.,Ltd ‐3‐ www.feasycom.com

FSC‐BT630 Datasheet Module picture as below showing Figure 1: FSC‐BT630 Picture Shenzhen Feasycom Technology Co.,Ltd ‐4‐ www.feasycom.com

FSC‐BT630 Datasheet 2. General Specification Table 1: General Specifications Categories Features Implementation Bluetooth Version Bluetooth low energy (BLE) 4.2 and 5 Specifications Frequency 2.402 ‐ 2.480 GHz Transmit Power +4 dBm (Maximum) Wireless Receive Sensitivity ‐96 dBm sensitivity in Bluetooth low energy mode (Typical) Specification Antenna 2dBi Ceramic antenna Raw Data Rates (Air) 2 Mbps Bluetooth low energy mode 1 Mbps, 2 Mbps supported data rates TX,RX,CTS/RTS(with EasyDMA) General Purpose I/O UART Interface Default 115200,N,8,1 Baudrate support from 1200 to 921600 5, 6, 7, 8 data bit character(TBD) 13 (maximum – configurable) lines O/P drive strength (2~10 mA) GPIO Pull‐up resistor (13 KΩ) control Read pin‐level Up to 2x I2C compatible 2‐Wire master/slave I2C Interface (configurable from GPIO total) Up to 400 kbps(master) Supports Master or Slave mode operation Simultaneous bi‐directional (TX and RX) audio streaming Original I2S and left‐ or right‐aligned format I2S Interface Host Interface and 8, 16 and 24‐bit sample width Peripherals Low‐jitter Master Clock generator Various sample rates Analog input voltage range: 0~ VDD (VDD=3.6V) 8/10/12‐bit resolution, 14‐bit resolution with oversampling ADC Interface 6 channels (configured from GPIO total) Up to 200 ksps conversion 16‐bit resolution 8‐bit prescaler and clock divider PWM Supports PWM interrupts supports input capture function Up to two PDM microphones configured as a Left/Right pair using the same data input PDM 16 kHz output sample rate, 16‐bit samples EasyDMA support for sample buffering HW decimation filters NFC‐A 13.56 MHz input frequency Shenzhen Feasycom Technology Co., Ltd ‐5‐ www.feasycom.com

FSC‐BT630 Datasheet listen mode operation Bit rate 106 kbps 3 SPI instances(configurable from GPIO total) SPI SPI Slave and SPI Master Bit rates for SPI Slave and Master ‐ 8 Mbps Temperature range is greater than or equal to operating temperature Temperature sensor of the device Resolution is 0.25 degrees Classic Bluetooth No Support Bluetooth Low Energy GATT Client & Peripheral ‐ Any Custom Services Profiles BT5 Specifications MFI Support Maximum Classic Bluetooth No Support Connections Bluetooth Low Energy 1Clients(TBD) Over the Air FW upgrade Via UART J‐link Supply Voltage Supply 1.7 ~ 3.6V 5.3 mA peak current in TX (0 dBm) 6.6 mA peak current in TX (4 dBm)(TBD) 5.4 mA peak current in RX Power Consumption ~0.3uA ‐ System OFF current, no RAM retention ~1.2uA ‐ System ON base current, no RAM retention ~20nA ‐ Additional RAM retention current per 4 KB RAM section Power fail comparator <4uA ‐ Current consumption when enabled Physical Dimensions 10mm X 11.9mm X 1.7mm; Pad Pitch 1.1mm Operating ‐40°C to +85°C Environmental Storage ‐40°C to +125°C Lead Free Lead‐free and RoHS compliant Warranty One Year Miscellaneous Flash memory Endurance: 10000(Write/erase cycles) Retention: 10 years at 40°C Humidity 10% ~ 90% non‐condensing MSL grade: MSL 1 ESD HBM: 2KV ESD grade: ESD CDM: 500V Shenzhen Feasycom Technology Co., Ltd ‐6‐ www.feasycom.com

FSC‐BT630 Datasheet 3. HARDWARE SPECIFICATION 3.1 PIN Definition Descriptions Table 2: Pin definition Pin Pin Name Type Pin Descriptions Notes 1 UART_TX O UART Data output Note 1 2 UART_RX I UART Data input Note 1 3 PIO0/I2C_SDA I/O Programmable input/output line Note 2,3 4 PIO1/I2C_SCL I/O Programmable input/output line Note 2,3 5 PIO2/AIO0/TRAN I/O Programmable input/output line Note Alternative Function 1: Analogue programmable I/O line. 2,4 Alternative Function 2: Host MCU change UART transmission mode. 6 RESET I External reset input: Active LOW, with an inter an internal pull‐up. Note 3 Set this pin low reset to initial state. 7 VDD_3V3 Vdd Power supply voltage 1.7 ~ 3.6V(default 3.3V) 8 GND Vss Power Ground 9 SWCLK I Serial wire debug clock input for debugand programming 10 SWDIO I/O Serial wire debug I/O for debug and programming 11 PIO3/I2S_LRCK I/O Programmable input/output line Note 2 Alternative Function 1: I2S left right channel clock Alternative Function 2: Analogue programmable I/O line. 12 PIO4/I2S_SD_IN I Programmable input/output line Note 2 Alternative Function 1: I2S data input Alternative Function 2: Analogue programmable I/O line. 13 PIO5/I2S_SD_OUT O Programmable input/output line Note 2 Alternative Function 1: I2S data out Alternative Function 2: Analogue programmable I/O line. 14 PIO6/I2S_BCLK I/O Programmable input/output line Note 2 Alternative Function 1: I2S bit clock pin Alternative Function 2: Analogue programmable I/O line. 15 PIO7/AIO1/DISC/I2S_MC I/O Programmable input/output line Note LK Alternative Function 1: Analogue programmable I/O line. 2,5 Alternative Function 2: I2S Master clock pin. Alternative Function 3: Host MCU disconnect bluetooth. Alternative Function 4: Analogue programmable I/O line. 16 PIO8/MUTE I/O Programmable input/output line Note 6 Alternative Function: Mute Pin 17 PIO9/LED/NFC2 I/O Programmable input/output line Note 7 Alternative Function 1: LED Shenzhen Feasycom Technology Co., Ltd ‐7‐ www.feasycom.com

FSC‐BT630 Datasheet Alternative Function 2: NFC2 18 PIO10/STATUS/NFC1 I/O Programmable input/output line Note 8 Alternative Function 1: BT Status Alternative Function 2: NFC1 19 GND Vss Power Ground 20 EXT_ANT O RF signal output . Note 9 Module Pin Notes: Note 1 For customized module, this pin can be work as I/O Interface. Note 2 I2C/PWM/SPI/PDM/UART(CTS/RTS) with EasyDMA (Support accomplishing the port mapping to other spare I/O Interface via modifying the firmware.) Note 3 I2C Serial Clock and Data. It is essential to remember that pull‐up resistors on both SCL and SDA lines are not provided in the module and MUST be provided external to the module. Note 4 When bluetooth connection established, UART transmission mode will be determined by PIO2's level : High: Command Mode Low: Throughput Mode Note 5 When bluetooth connection established,a riging edge of PIO7 will cause disconnection with remote device. Note 6 Audio Mute Pin‐‐ Mute ON: High Level; Mute OFF: Low Level. Note 7 LED(Default)‐‐ Power On: Light Slow Shinning ; Connected: Steady Lighting. Note 8 BT Status(Default)‐‐ Disconnected: Low Level; Connected: High Level. Note 9 By default, this PIN is an empty feet. This PIN can connect to an external antenna to improve the Bluetooth signal coverage. If you need to use an external antenna, by modifying the module on the 0R resistance to block out the on‐board antenna; Or contact Feasycom for modification. 4. PHYSICAL INTERFACE 4.1 Power Supply The transient response of the regulator is important. If the power rails of the module are supplied from an external voltage source, the transient response of any regulator used should be 20μs or less. It is essential that the power rail recovers quickly. This module has the following power supply features: On‐chip LDO and DC/DC regulators Global System ON/OFF modes Individual RAM section power control for all system modes Analog or digital pin wakeup from System OFF Supervisor HW to manage power on reset, brownout, and power fail Auto‐controlled refresh modes for LDO and DC/DC regulators to maximize efficiency Automatic switching between LDO and DC/DC regulator based on load to maximize efficiency Shenzhen Feasycom Technology Co., Ltd ‐8‐ www.feasycom.com

FSC‐BT630 Datasheet 4.2 Reset The module may be reset from several sources: Power‐on Reset (POR), Low level on the nRESET Pin (nRST), Watchdog time‐out reset (WDT), Wakeup from System OFF mode reset , Brown‐out reset or Software Reset(SYSRESETREQ, CPU Reset, CHIPRST). The RESET pin is an active low reset and is internally filtered using the internal low frequency clock oscillator. A reset will be performed between 1.5 and 4.0ms following RESET being active. It is recommended that RESET be applied for a period greater than 5ms. At reset the digital I/O pins are set to inputs for bi‐directional pins and outputs are tri‐state. The PIOs have weak pull‐ups. Table 3: NRST pin characteristics Parameter Conditions Min Typ Max Unit RPU ‐ Weak pull‐up equivalent resistor(1) VIN = VSS 30 40 50 KΩ VF(NRST)(2) ‐ NRST Input filtered pulse ‐ ‐ 100 ns VNF(NRST)(2) ‐ NRST Input not filtered pulse VDD>1.2V 300 ‐ ‐ ns TNRST_OUT ‐ Generated reset pulse duration Internal Reset source 20 ‐ ‐ μs VPOF ‐ Nominal power level warning 1.7 2.8 V thresholds (falling supply voltage). Levels are configurable between Min. and Max. in 100mV increments. VBOR,OFF ‐ Brown out reset voltage range 1.2 1.7 V SYSTEM OFF mode VBOR,ON ‐ Brown out reset voltage range 1.5 1.7 V SYSTEM ON mode 1. The pull‐up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). 2. Guaranteed by design. 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in NRST pin characteristics. Otherwise the reset is not taken into account by the device. 4.3 General Purpose Analog IO The ADC is a differential successive approximation register (SAR) analog‐to‐digital converter. Listed here are the main features of SAADC: 8/10/12‐bit resolution, 14‐bit resolution with oversampling Up to eight input channels Shenzhen Feasycom Technology Co., Ltd ‐9‐ www.feasycom.com

FSC‐BT630 Datasheet • One channel per single‐ended input and two channels per differential input • Scan mode can be configured with both single‐ended channels and differential channels. Full scale input range (0 to VDD) Sampling triggered via a task from software or a PPI channel for full flexibility on sample frequency source from low power 32.768kHz RTC or more accurate 1/16MHz Timers One‐shot conversion mode to sample a single channel Scan mode to sample a series of channels in sequence. Sample delay between channels is tack + tconv which may vary between channels according to user configuration of tack. Support for direct sample transfer to RAM using EasyDMA Interrupts on single sample and full buffer events Samples stored as 16‐bit 2’s complement values for differential and single‐ended sampling Continuous sampling without the need of an external timer Internal resistor string Limit checking on the fly 4.4 General Purpose Digital IO There are 13 general purpose digital IOs defined in the module. All these GPIOs can be configured by software to realize various functions, such as button controls, LED drives or interrupt signals to host controller, etc. Do not connect them if not use. The I/O type of each I/O pins can be configured by software individually as Input or Push‐pull output mode. After the chip is reset, the I/O mode of all pins is input mode with no pull‐up and pull‐down enable. Each I/O pin has an individual pull‐up and pull‐down resistor which is about 40 kΩ for VDD and Vss. Configurable output drive strength Internal pull‐up and pull‐down resistors Wake‐up from high or low level triggers on all pins Trigger interrupt on state changes on any pin All pins can be used by the PPI task/event system One or more GPIO outputs can be controlled through PPI and GPIOTE channels All pins can be individually mapped to interface blocks for layout flexibility GPIO state changes captured on SENSE signal can be stored by LATCH register 4.5 I2S Interfaces The I2S (Inter‐IC Sound) module, supports the original two‐channel I2S format, and left or right‐aligned formats. It implements EasyDMA for sample transfer directly to and from RAM without CPU intervention. The I2S peripheral has the following main features: Master and Slave mode Simultaneous bi‐directional (TX and RX) audio streaming Original I2S and left‐ or right‐aligned format Shenzhen Feasycom Technology Co., Ltd ‐10‐ www.feasycom.com

FSC‐BT630 Datasheet 8, 16 and 24‐bit sample width Low‐jitter Master Clock generator Various sample rates 4.6 SPI Interfaces The SPI master provides a simple CPU interface which includes a TXD register for sending data and an RXD register for receiving data. This section is added for legacy support for now. The TXD and RXD registers are double-buffered to enable some degree of uninterrupted data flow in and out of the SPI master. The SPI master does not implement support for chip select directly. Therefore, the CPU must use available GPIOs to select the correct slave and control this independently of the SPI master. The SPI master supports SPI modes 0 through 3. 4.7 RF Interface For this Module, the default mode for antenna is internal ,it also has the interface for external antenna. If you need to use an external antenna, by modifying the module on the 0R resistance to block out the on‐board antenna; Or contact Feasycom for modification.The user can connect a 50 ohm antenna directly to the RF port. 2402–2480 MHz Bluetooth 4.2 and Bluetooth 5 2 Mbps Bluetooth low energy mode 1 Mbps, 2 Mbps supported data rates TX power ‐20 to +4 dBm in 4 dB steps ‐96 dBm sensitivity in Bluetooth® low energy mode Single‐pin antenna interface RSSI (1 dB resolution) The RADIO includes a Device Address Match unit and an interframe spacing control unit that can be utilized to simplify address white listing and interframe spacing respectively, in Bluetooth Smart and similar applications. The RADIO also includes a Received Signal Strength Indicator (RSSI) and a bit counter. The bit counter generates events when a preconfigured number of bits have been sent or received by the RADIO. 4.8 Serial Interfaces 4.8.1 UART FSC‐BT630 provides one channels of Universal Asynchronous Receiver/Transmitters(UART)(Full‐duplex asynchronous communications). The UART Controller performs a serial‐to‐parallel conversion on data received from the peripheral and a parallel‐to‐serial conversion on data transmitted from the CPU. Each UART Controller channel supports ten types of interrupts. Shenzhen Feasycom Technology Co., Ltd ‐11‐ www.feasycom.com

FSC‐BT630 Datasheet This is a standard UART interface for communicating with other serial devices. The UART interface provides a simple mechanism for communicating with other serial devices using the RS232 protocol. When the module is connected to another digital device, UART_RX and UART_TX transfer data between the two devices. The remaining two signals, UART_CTS and UART_RTS, can be used to implement RS232 hardware flow control where both are active low indicators. This module output is at 3.3V CMOS logic levels (tracks VCC). Level conversion must be added to interface with an RS‐232 level compliant interface. Some serial implementations link CTS and RTS to remove the need for handshaking. We do not recommend linking CTS and RTS except for testing and prototyping. If these pins are linked and the host sends data when the FSC‐BT630 deasserts its RTS signal, there is significant risk that internal receive buffers will overflow, which could lead to an internal processor crash. This drops the connection and may require a power cycle to reset the module. We recommend that you adhere to the correct CTS/RTS handshaking protocol for proper operation. Full‐duplex operation Automatic hardware flow control Parity checking and generation for the 9th data bit EasyDMA Up to 1 Mbps baudrate Return to IDLE between transactions supported (when using HW flow control) One stop bit Least significant bit (LSB) first The GPIOs used for each UART interface can be chosen from any GPIO on the device and are independently configurable. This enables great flexibility in device pinout and efficient use of board space and signal routing. Table 4: Possible UART Settings Parameter Possible Values Minimum 1200 baud (≤2%Error) Baudrate Standard 115200bps(≤1%Error) Maximum 921600bps(≤1%Error) Flow control RTS/CTS, or None Parity None, Odd or Even Number of stop bits 1 Bits per channel 8 When connecting the module to a host, please make sure to follow . 4.8.2 I2C Interface I2C is a two‐wire, bi‐directional serial bus that provides a simple and efficient method of data exchange between devices. The I2C standard is a true multi‐master bus including collision detection and arbitration that prevents data Shenzhen Feasycom Technology Co., Ltd ‐12‐ www.feasycom.com

FSC‐BT630 Datasheet corruption if two or more masters attempt to control the bus simultaneously. Data is transferred between a Master and a Slave synchronously to SCL on the SDA line on a byte‐by‐byte basis. Each data byte is 8‐bit long. There is one SCL clock pulse for each data bit with the MSB being transmitted first. An acknowledge bit follows each transferred byte. Each bit is sampled during the high period of SCL; therefore, the SDA line may be changed only during the low period of SCL and must be held stable during the high period of SCL. A transition on the SDA line while SCL is high is interpreted as a command (START or STOP). Please refer to the following figure for more details about I2C Bus Timing. The device on‐chip I2C logic provides the serial interface that meets the I2C bus standard mode specification. The I2C port handles byte transfers autonomously. The I2C H/W interfaces to the I2C bus via two pins: SDA and SCL. Pull up resistor is needed for I2C operation as these are open drain pins. When the I/O pins are used as I2C port, user must set the pins function to I2C in advance. The I2C master is compatible with I2C operating at 100 kHz and 400 kHz. 4.9 Pulse width modulation (PWM) The PWM module enables the generation of pulse width modulated signals on GPIO. The module implements an up or up‐and‐down counter with four PWM channels that drive assigned GPIOs. Three PWM modules can provide up to 12 PWM channels with individual frequency control in groups of up to four channels. Furthermore, a built‐in decoder and EasyDMA capabilities make it possible to manipulate the PWM duty cycles without CPU intervention. Arbitrary duty‐cycle sequences are read from Data RAM and can be chained to implement ping‐pong buffering or repeated into complex loops. Listed here are the main features of one PWM module: Fixed PWM base frequency with programmable clock divider Up to four PWM channels with individual polarity and duty‐cycle values Edge or center‐aligned pulses across PWM channels Multiple duty‐cycle arrays (sequences) defined in Data RAM Autonomous and glitch‐free update of duty cycle values directly from memory through EasyDMA Change of polarity, duty‐cycle, and base frequency possibly on every PWM period Data RAM sequences can be repeated or connected into loops 4.10 Pulse density modulation interface (PDM) The pulse density modulation (PDM) module enables input of pulse density modulated signals from external audio frontends, for example, digital microphones. The PDM module generates the PDM clock and supports single‐channel or dual‐channel (Left and Right) data input. Data is transferred directly to RAM buffers using EasyDMA. Listed here are the main features for PDM: Up to two PDM microphones configured as a Left/Right pair using the same data input 16 kHz output sample rate, 16‐bit samples EasyDMA support for sample buffering Shenzhen Feasycom Technology Co., Ltd ‐13‐ www.feasycom.com

FSC‐BT630 Datasheet HW decimation filters The PDM module illustrated The PDM module illustrated is interfacing up to two digital microphones with the PDM interface. It implements EasyDMA, which relieves real‐time requirements associated with controlling the PDM slave from a low priority CPU execution context. It also includes all the necessary digital filter elements to produce PCM samples. The PDM module allows continuous audio streaming. 4.10.1 Hardware example Connect the microphone clock to CLK, and data to DIN. Note that in a single-microphone (mono) configuration, depending on the microphone’s implementation, either the left or the right channel (sampled at falling or rising CLK edge respectively) will contain reliable data. If two microphones are used, one of them has to be set as left, the other as right (L/R pin tied high or to GND on the respective microphone). It is strongly recommended to use two microphones of exactly the same brand and type so that their timings in left and right operation match. 4.11 Near field communication tag (NFC) The NFC peripheral (referred to as the 'NFC peripheral' from now on) supports communication signal interface type A and 106 kbps bit rate from the NFC Forum. With appropriate software, the NFC peripheral can be used to emulate the listening device NFC‐A as specified by the NFC Forum. Listed here are the main features for the NFC peripheral: NFC‐A listen mode operation • 13.56 MHz input frequency • Bit rate 106 kbps Wake‐on‐field low power field detection (SENSE) mode Frame assemble and disassemble for the NFC‐A frames specified by the NFC Forum Programmable frame timing controller Integrated automatic collision resolution, CRC and parity functions 4.11.1 Antenna interface In ACTIVATED state, an amplitude regulator will adjust the voltage swing on the antenna pins to a value that is within the Vswing limit. Shenzhen Feasycom Technology Co., Ltd ‐14‐ www.feasycom.com

FSC‐BT630 Datasheet 4.11.2 NFCT antenna recommendations The NFCT antenna coil must be connected differential between NFC1 and NFC2 pins of the device. Two external capacitors should be used to tune the resonance of the antenna circuit to 13.56MHz. The required tuning capacitor value is given by the below equations: An antenna inductance of Lant = 2 μH will give tuning capacitors in the range of 130pF on each pin. For good performance, match the total capacitance on NFC1 and NFC2. 4.11.3 Battery protection If the antenna is exposed to a strong NFC field, current may flow in the opposite direction on the supply due to parasitic diodes and ESD structures. If the battery used does not tolerate return current, a series diode must be placed between the battery and the device in order to protect the battery. 4.11.4 References NFC Forum, NFC Analog Specification version 1.0, www.nfc‐forum.org NFC Forum, NFC Digital Protocol Technical Specification version 1.1, www.nfc‐forum.org NFC Forum, NFC Activity Technical Specification version 1.1, www.nfc‐forum.org 5. ELECTRICAL CHARACTERISTICS 5.1 Absolute Maximum Ratings Absolute maximum ratings for supply voltage and voltages on digital and analogue pins of the module are listed below. Exceeding these values causes permanent damage. The average PIO pin output current is defined as the average current value flowing through any one of the Shenzhen Feasycom Technology Co., Ltd ‐15‐ www.feasycom.com

FSC‐BT630 Datasheet corresponding pins for a 100mS period. The total average PIO pin output current is defined as the average current value flowing through all of the corresponding pins for a 100mS period. The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. Table 5: Absolute Maximum Rating Parameter Min Max Unit Supply voltages VDD ‐0.3 +3.9V V VSS 0V V I/O pin voltage VI/O, VDD ≤3.6 V ‐0.3 VDD+0.3 V VI/O, VDD >3.6 V ‐0.3 3.9V V NFC antenna pin current INFC1/2 80 mA Radio RF input level 10 dBm Environmental Storage temperature ‐40 +125 °C 5.2 Recommended Operating Conditions Table 6: Recommended Operating Conditions Parameter Min Type Max Unit VDD ‐ Supply voltage, independent of DCDC enable 1.7 3.0 3.6 V tR_VDD ‐ Supply rise time (0 V to 1.7 V) 60 mS TA ‐ Operating Temperature ‐40 25 +85 °C Important: The on‐chip power‐on reset circuitry may not function properly for rise times longer than the specified maximum. 5.3 Input/output Terminal Characteristics Table 7: GPIO Electrical Specification Parameter Min Type Max Unit VIH ‐ Input High Voltage 0.7xVDD ‐ VDD V VIL ‐ Input Low Voltage VSS ‐ 0.3xVDD V VOH,HDH ‐ Output high voltage, standard drive, 0.5 mA, VDD ≥1.7 VDD‐0.4 ‐ VDD V VOH,HDH ‐ Output high voltage, high drive, 5 mA, VDD >= 2.7 V VDD‐0.4 ‐ VDD V VOH,HDL ‐ Output high voltage, high drive, 3 mA, VDD >= 1.7 V VDD‐0.4 ‐ VDD V VOL,SD ‐ Output low voltage, standard drive, 0.5 mA, VDD ≥1.7 VSS ‐ VSS+0.4 V VOL,HDH ‐ Output low voltage, high drive, 5 mA, VDD >= 2.7 V VSS ‐ VSS+0.4 V Shenzhen Feasycom Technology Co., Ltd ‐16‐ www.feasycom.com

FSC‐BT630 Datasheet VOL,HDL ‐ Output low voltage, high drive, 3 mA, VDD >= 1.7 V VSS ‐ VSS+0.4 V IOL,SD ‐ Current at VSS+0.4 V, output set low, standard drive, VDD 1 2 4 mA ≥1.7 IOL,HDH ‐ Current at VSS+0.4 V, output set low, high drive, VDD >= 6 10 15 mA 2.7 V IOL,HDL ‐ Current at VSS+0.4 V, output set low, high drive, VDD >= 3 ‐ ‐ mA 1.7 V IOH,SD ‐ Current at VDD‐0.4 V, output set high, standard drive, 1 2 4 mA VDD ≥1.7 IOH,HDH ‐ Current at VDD‐0.4 V, output set high, high drive, 6 9 14 mA VDD >= 2.7 V IOH,HDL ‐ Current at VDD‐0.4 V, output set high, high drive, VDD >= 3 ‐ ‐ mA 1.7 V tRF,15pF ‐ Rise/fall time, low drive mode, 10‐90%, 15 pF load1 ‐ 9 ‐ nS tRF,25pF ‐ Rise/fall time, low drive mode, 10‐90%, 25 pF load1 ‐ 13 ‐ nS tRF,50pF ‐ Rise/fall time, low drive mode, 10‐90%, 50 pF load1 ‐ 25 ‐ nS tHRF,15pF ‐ Rise/Fall time, high drive mode, 10‐90%, 15 pF load1 ‐ 4 ‐ nS tHRF,25pF ‐ Rise/Fall time, high drive mode, 10‐90%, 25 pF load1 ‐ 5 ‐ nS tHRF,50pF ‐ Rise/Fall time, high drive mode, 10‐90%, 50 pF load1 ‐ 8 ‐ nS RPU ‐ Pull‐up resistance 11 13 16 KΩ RPD ‐ Pull‐down resistance 11 13 16 KΩ CPAD ‐ Pad capacitance ‐ 3 ‐ pF CPAD_NFC ‐ Pad capacitance on NFC pads ‐ 4 ‐ pF INFC_LEAK ‐ Leakage current between NFC pads when driven to ‐ 2 10 uA different states The current drawn from the battery when GPIO is active as an output is calculated as follows: IGPIO=VDD Cload f Cload being the load capacitance and “f” is the switching frequency. Shenzhen Feasycom Technology Co., Ltd ‐17‐ www.feasycom.com

FSC‐BT630 Datasheet GPIO drive strength vs Voltage, standard drive, VDD = 3.0 V GPIO drive strength vs Voltage, high drive, VDD = 3.0 V Max sink current vs Voltage, standard drive Max sink current vs Voltage, high drive Shenzhen Feasycom Technology Co., Ltd ‐18‐ www.feasycom.com

FSC‐BT630 Datasheet Rise and fall time vs Temperature, 10%‐90%, 25pF load capacitance, VDD = 3.0 V 5.4 Analog Characteristics 5.4.1 ADC Electrical Specification Table 8: ADC characteristics Parameter Min Typ Max Unit DNL ‐ Differential non‐linearity, 10‐bit resolution ‐0.95 <1 ‐ LSB INL ‐ Integral non‐linearity, 10‐bit resolution ‐ 1 ‐ LSB VOS ‐ Differential offset error (calibrated), 10‐bit resolution a ‐ +‐2 ‐ LSB CEG ‐ Gain error temperature coefficient ‐ 0.02 ‐ %/°C fSAMPLE ‐ Maximum sampling rate ‐ ‐ 200 kHz tACQ,10k ‐ Acquisition time (configurable), source Resistance <= 10kOhm ‐ 3 ‐ μs tACQ,40k ‐ Acquisition time (configurable), source Resistance <= 40kOhm ‐ 5 ‐ μs tACQ,100k ‐ Acquisition time (configurable), source Resistance <= 100kOhm ‐ 10 ‐ μs tACQ,200k ‐ Acquisition time (configurable), source Resistance<=200kOhm ‐ 15 ‐ μs tACQ,400k ‐ Acquisition time (configurable), source Resistance <= 400kOhm ‐ 20 ‐ μs tACQ,800k ‐ Acquisition time (configurable), source Resistance <= 800kOhm ‐ 40 ‐ μs tCONV ‐ Conversion time ‐ <2 ‐ μs IADC,CONV ‐ ADC current during ACQuisition and CONVersion ‐ 700 ‐ μA IADC,IDLE ‐ Idle current, when not sampling, excluding clock sources and ‐ <5 ‐ μA regulator base currents33 EG1/6 ‐ Errorb for Gain = 1/6 ‐3 ‐ 3 % EG1/4 ‐ Errorb for Gain = 1/4 ‐3 ‐ 3 % EG1/2 ‐ Errorb for Gain = 1/2 ‐3 ‐ 4 % EG1 ‐ Errorb for Gain = 1 ‐3 ‐ 4 % CSAMPLE ‐ Sample and hold capacitance at maximum gain ‐ 2.5 ‐ pF RINPUT ‐ Input resistance ‐ >1 ‐ MΩ Shenzhen Feasycom Technology Co., Ltd ‐19‐ www.feasycom.com

FSC‐BT630 Datasheet ENOB ‐ Effective number of bits, differential mode, 12‐bit resolution, ‐ 9 ‐ Bit 1/1 gain, 3 μs acquisition time, crystal HFCLK, 200 ksps SNDR ‐ Peak signal to noise and distortion ratio, differential mode, 12‐ ‐ 56 ‐ dB bit resolution, 1/1 gain, 3 μs acquisition time, crystal HFCLK, 200ksps SFDR ‐ Spurious free dynamic range, differential mode, 12‐bit ‐ 70 ‐ dBc resolution, 1/1 gain, 3 μs acquisition time, crystal HFCLK, 200ksps RLADDER ‐ Ladder resistance ‐ 160 ‐ kΩ a :Digital output code at zero volt differential input. 33 :When tACQ is 10us or longer, and if DC/DC is active, it will be allowed to work in refresh mode if no other resource is requiring a high quality power supply from 1V3. If tACQ is smaller than 10us and DC/DC is active, Note: SAADC average current calculation for a given application is based on the sample period, conversion and acquisition time ( tconv and tACQ) and conversion and idle current (IADC,CONV and IADC,IDLE). For example,sampling at 4kHz gives a sample period of 250μs. The average current consumption would then be: Typical connection diagram using the ADC 5.5 SPI Electrical specification 5.5.1 SPI master interface Table 9: SPI master interface electrical specifications Parameter Min Typ Max Unit fSPI ‐ Bit rates for SPIa ‐ ‐ 8b Mbps ISPI,2Mbps ‐ Run current for SPI, 2 Mbps ‐ ‐ 50 μA ISPI,8Mbps ‐ Run current for SPI, 8 Mbps ‐ ‐ 50 μA ISPI,IDLE Idle ‐ current for SPI (STARTed, no CSN activity) ‐ <1 ‐ μA tSPI,START,LP ‐ Time from writing TXD register to transmission started, low tSPI,START,CL power mode ‐ + ‐ μS tSTART_HFINT Shenzhen Feasycom Technology Co., Ltd ‐20‐ www.feasycom.com

FSC‐BT630 Datasheet tSPI,START,CL ‐ Time from writing TXD register to transmission started, uS ‐ 1 ‐ constant latency mode a:Higher bit rates may require GPIOs to be set as High Drive, see GPIO chapter for more details. b:The actual maximum data rate depends on the slave's CLK to MISO and MOSI setup and hold timings. Table 10: Serial Peripheral Interface (SPI) Master timing specifications Parameter Min Typ Max Unit tSPI,CSCK,8Mbps ‐ SCK period at 8Mbps ‐ 125 ‐ nS tSPI,CSCK,4Mbps ‐ SCK period at 4Mbps ‐ 250 ‐ nS tSPI,CSCK,2Mbps ‐ SCK period at 2Mbps ‐ 500 ‐ nS tSPI,RSCK,LD ‐ SCK rise time, low drivea ‐ ‐ tRF,25pF tSPI,RSCK,HD ‐ SCK rise time, high drivea ‐ ‐ tHRF,25pF tSPI,FSCK,LD ‐ SCK fall time, low drivea ‐ ‐ tRF,25pF tSPI,FSCK,HD ‐ SCK fall time, high drivea ‐ ‐ tHRF,25pF tSPI,WHSCK ‐ SCK high timea (0.5*tCSCK) – tRSCK tSPI,WLSCK ‐ SCK low timea (0.5*tCSCK) – tFSCK tSPI,SUMI ‐ MISO to CLK edge setup time 19 ns tSPI,HMI ‐ CLK edge to MISO hold time 18 ns tSPI,VMO ‐ CLK edge to MOSI valid 59 ns tSPI,HMO ‐ MOSI hold time after CLK edge 20 ns a: At 25pF load, including GPIO capacitance, see GPIO spec. 5.5.2 SPI slave interface electrical specifications Table 11: SPI slave interface electrical specifications Parameter Min Typ Max Unit fSPI ‐ Bit rates for SPIa ‐ ‐ 8b Mbps ISPI,2Mbps ‐ Run current for SPI, 2 Mbps ‐ 45 ‐ μA ISPI,8Mbps ‐ Run current for SPI, 8 Mbps ‐ 45 ‐ μA ISPI,IDLE Idle ‐ current for SPI (STARTed, no CSN activity) ‐ 1 ‐ μA tSPIS,LP,START ‐ Time from RELEASE task to ready to receive/transmit (CSN tSPIS,CL,START active), Low power mode ‐ + ‐ μS tSTART_HFINT tSPIS,CL,START ‐ Time from RELEASE task to receive/transmit (CSN active), ‐ 0.125 ‐ uS Shenzhen Feasycom Technology Co., Ltd ‐21‐ www.feasycom.com

FSC‐BT630 Datasheet Constant latency mode a:Higher bit rates may require GPIOs to be set as High Drive, see GPIO chapter for more details. b:The actual maximum data rate depends on the slave's CLK to MISO and MOSI setup and hold timings. Table 12: Serial Peripheral Interface Slave (SPIS) timing specifications Parameter Min Typ Max Unit tSPI,CSCK,8Mbps ‐ SCK period at 8Mbps ‐ 125 ‐ nS tSPI,CSCK,4Mbps ‐ SCK period at 4Mbps ‐ 250 ‐ nS tSPI,CSCK,2Mbps ‐ SCK period at 2Mbps ‐ 500 ‐ nS tSPIS,RFSCKIN ‐ SCK input rise/fall time 30 nS tSPIS,WHSCKIN ‐ SCK input high time 30 nS tSPIS,WLSCKIN ‐ SCK input low time 30 nS tSPIS,SUCSN,LP ‐ CSN to CLK setup time, Low power mode tSPIS,SUCSN,CL + nS tSTART_HFINT tSPIS,SUCSN,CL‐ CSN to CLK setup time, Constant latency mode 1000 nS tSPIS,HCSN ‐ CLK to CSN hold time 2000 nS tSPIS,ASO ‐ CSN to MISO drivena 1000 nS tSPIS,DISSO ‐ CSN to MISO disableda 68 nS tSPIS,CWH ‐ CSN inactive time 300 nS tSPIS,VSO ‐ CLK edge to MISO valid 19 nS tSPIS,HSO ‐ MISO hold time after CLK edge 18b nS tSPIS,SUSI‐ MOSI to CLK edge setup time 59 nS tSPIS,HSI ‐ CLK edge to MOSI hold time 20 nS a: At 25pF load, including GPIO capacitance, see GPIO spec. b: This is to ensure compatibility to SPI masters sampling MISO on the same edge as MOSI is output 5.6 I2C Dynamic Characteristics 5.6.1 I2C Master interface electrical specifications Table 13: I2C interface electrical specifications(Master) Parameter Min Typ Max Unit fI2C ‐ Bit rates for I2Ca 100 ‐ 400 Kbps II2C,100kbps ‐ Run current for I2C, 100 kbps ‐ 50 ‐ μA II2C,400kbps ‐ Run current for I2C, 400 kbps ‐ 50 ‐ μA tI2C,START,LP ‐ Time from STARTRX/STARTTX task to transmission started, TI2C,START,CL Low power mode ‐ + ‐ μS tSTART_HFINT Shenzhen Feasycom Technology Co., Ltd ‐22‐ www.feasycom.com

FSC‐BT630 Datasheet tI2C,START,CL ‐ Time from STARTRX/STARTTX task to transmission started, ‐ 1.5 ‐ μS Constant latency mode a: Higher bit rates or stronger pull‐ups may require GPIOs to be set as High Drive, see GPIO chapter for more details. Table 14: Two Wire Interface (I2C) timing specifications(Master) Parameter Min Typ Max Unit fI2C,SCL,100kbps ‐ SCL clock frequency, 100 kbps ‐ 100 KHz fI2C,SCL,250kbps ‐ SCL clock frequency, 250 kbps ‐ 250 ‐ KHz fI2C,SCL,400kbps ‐ SCL clock frequency, 400 kbps ‐ 400 ‐ KHz tI2C,SU_DAT ‐ Data setup time before positive edge on SCL – all modes 300 ‐ ‐ nS tI2C,HD_DAT ‐ Data hold time after negative edge on SCL – all modes 500 ‐ ‐ nS tI2C,HD_STA,100kbps ‐ I2C master hold time for START and repeated START ‐ ‐ nS 10000 condition, 100 kbps tI2C,HD_STA,250kbps ‐ I2C master hold time for START and repeated START ‐ ‐ nS 4000 condition, 250kbps tI2C,HD_STA,400kbps‐ I2C master hold time for START and repeated START ‐ ‐ nS 2500 condition,400 kbps tI2C,SU_STO,100kbps ‐ I2C master setup time from SCL high to STOP condition, ‐ ‐ nS 5000 100kbps tI2C,SU_STO,250kbps ‐ I2C master setup time from SCL high to STOP condition, ‐ ‐ nS 2000 250kbps tI2C,SU_STO,400kbps ‐ I2C master setup time from SCL high to STOP condition, ‐ ‐ nS 1250 400kbps tI2C,BUF,100kbps ‐ I2C master bus free time between STOP and START ‐ ‐ nS 5800 conditions,100 kbps tI2C,BUF,250kbps ‐ I2C master bus free time between STOP and START ‐ ‐ nS 2700 conditions,250 kbps tI2C,BUF,400kbps ‐ I2C master bus free time between STOP and START ‐ ‐ nS 2100 conditions,400 kbps Shenzhen Feasycom Technology Co., Ltd ‐23‐ www.feasycom.com

FSC‐BT630 Datasheet Recommended TWIM pullup value vs. line capacitance • The I2C specification allows a line capacitance of 400 pF at most. • FSC‐BT630 internal pullup has a fixed value of typ. 13 kOhm, see RPU in the GPIO chapter. 5.6.2 I2C slave interface electrical specifications Table 15: I2C interface electrical specifications(Slave) Parameter Min Typ Max Unit fI2C ‐ Bit rates for I2Ca 100 ‐ 400 Kbps II2C,100kbps ‐ Run current for I2C, 100 kbps ‐ 45 ‐ μA II2C,400kbps ‐ Run current for I2C, 400 kbps ‐ 45 ‐ μA II2C,IDLE‐ Idle current for I2C ‐ 1 ‐ uA tI2C,START,LP ‐ Time from PREPARERX/PREPARETX task to transmission TI2C,START,CL started, Low power mode ‐ + ‐ μS tSTART_HFINT tI2C,START,CL ‐ Time from PREPARERX/PREPARETX task to transmission ‐ 1.5 ‐ μS started, Constant latency mode a: Higher bit rates or stronger pull‐ups may require GPIOs to be set as High Drive, see GPIO chapter for more details. Table 16: Two Wire Interface (I2C) timing specifications(Master) Parameter Min Typ Max Unit fI2C,SCL,400kbps ‐ SCL clock frequency, 400 kbps ‐ 400 ‐ KHz tI2C,SU_DAT ‐ Data setup time before positive edge on SCL – all modes 300 ‐ ‐ nS tI2C,HD_DAT ‐ Data hold time after negative edge on SCL – all modes 500 ‐ ‐ nS tI2C,HD_STA,100kbps ‐ I2C slave hold time from for START condition (SDA low to ‐ ‐ nS 5200 SCL Shenzhen Feasycom Technology Co., Ltd ‐24‐ www.feasycom.com

FSC‐BT630 Datasheet low), 100 kbps tI2C,HD_STA,400kbps‐ I2C slave hold time from for START condition (SDA low to ‐ ‐ nS 1300 SCL low), 400 kbps tI2C,SU_STO,100kbps ‐ I2C slave setup time from SCL high to STOP condition, ‐ ‐ nS 5200 100 kbps tI2C,SU_STO,400kbps ‐ I2C slave setup time from SCL high to STOP condition, ‐ ‐ nS 1300 400 kbps tI2C,BUF,100kbps ‐ I2C slave bus free time between STOP and START 4700 ‐ nS ‐ conditions, 100 kbps tI2C,BUF,400kbps ‐ I2C slave bus free time between STOP and START 1300 ‐ nS ‐ conditions, 400 kbps 5.7 I2S Electrical specification Table 17: I2S Dynamic Characteristics Parameter Min Typ Max Unit tS_SDIN ‐ SDIN setup time before SCK rising 20 ‐ 400 nS tH_SDIN ‐ SDIN hold time after SCK rising 15 50 ‐ nS tS_SDOUT ‐ SDOUT setup time after SCK falling 40 50 ‐ nS tH_SDOUT ‐ SDOUT hold time before SCK falling 6 ‐ ‐ nS tSCK_LRCK ‐ SCLK falling to LRCK edge ‐5 0 5 nS fMCK ‐ MCK frequency ‐ ‐ 4000 KHz fLRCK ‐ LRCK frequency ‐ ‐ 48 KHz fSCK ‐ SCK frequency ‐ ‐ 2000 KHz DCCK ‐ Clock duty cycle (MCK, LRCK, SCK) 45 ‐ 55 % 5.8 PWM Characteristics Table 18: PWM Electrical Specification Parameter Min Typ Max Unit IPWM,16MHz ‐ PWM run current, Prescaler set to DIV_1 (16 MHz), excluding ‐ 200 ‐ uA DMA and GPIO IPWM,8MHz‐ PWM run current, Prescaler set to DIV_2 (8 MHz), excluding ‐ uA ‐ 150 DMA and GPIO IPWM,125kHz ‐ PWM run current, Prescaler set to DIV_128 (125 kHz), ‐ uA ‐ 150 excluding DMA and GPIO 5.9 PDM Characteristics Table 19: PDM Electrical Specification Parameter Min Typ Max Unit Shenzhen Feasycom Technology Co., Ltd ‐25‐ www.feasycom.com

FSC‐BT630 Datasheet IPDM,stereo ‐ PDM module active current, stereo operationa ‐ 1.4 ‐ mA fPDM,CLK ‐ PDM clock speed ‐ 1.032 ‐ MHz tPDM,JITTER ‐ Jitter in PDM clock output ‐ ‐ 20 nS TdPDM,CLK ‐ PDM clock duty cycle 40 50 60 % tPDM,DATA ‐ Decimation filter delay ‐ ‐ 5 ms tPDM,cv ‐ Allowed clock edge to data valid ‐ ‐ 125 nS tPDM,ci ‐ Allowed (other) clock edge to data invalid 0 ‐ ‐ nS tPDM,s ‐ Data setup time at fPDM,CLK=1.024 MHz 65 ‐ ‐ nS tPDM,h ‐ Data hold time at fPDM,CLK=1.024 MHz 0 ‐ ‐ nS GPDM,default ‐ Default (reset) absolute gain of the PDM module ‐ 3.2 ‐ dB a: Average current including PDM and DMA transfers, excluding clock and power supply base currents 5.10 UART Electrical Specification Table 20: UART Electrical Specification Parameter Min Typ Max Unit fUART ‐ Baud rate for UARTa ‐ ‐ 1000 Kbps IUART1M ‐ Run current at max baud rate. ‐ 55 ‐ uA IUART115k ‐ Run current at 115200 bps. ‐ 55 ‐ uA IUART1k2‐ Run current at 1200 bps. ‐ 55 ‐ uA IUART,IDLE ‐ Idle current for UART ‐ 1 ‐ uA tUART,CTSH ‐ CTS high time 1 ‐ ‐ uS tUART,START,LP ‐ Time from STARTRX/STARTTX task to transmission started, tUART,START ‐ uS low power mode ‐ + tSTART_HFINT tUART,START,CL ‐ Time from STARTRX/STARTTX task to transmission started, ‐ uS ‐ 1 constant latency mode a: Higher baud rates may require GPIOs to be set as High Drive, see GPIO chapter for more details. 5.11 NFC Electrical Specification Table 21: NFC Electrical Specification Parameter Min Typ Max Unit fc ‐ Frequency of operation ‐ 13.56 ‐ MHz CMI ‐ Carrier modulation index 95 ‐ ‐ % DR ‐ Data Rate ‐ 106 ‐ kbps fs ‐ Modulation sub‐carrier frequency ‐ fc/16 ‐ MHz Vswing Peak differential Input voltage swing on NFC1 and NFC2 ‐ ‐ VDD Vp a Vsense ‐ Peak differential Field detect threshold level on NFC1‐NFC2 ‐ 1.0 ‐ Vp Shenzhen Feasycom Technology Co., Ltd ‐26‐ www.feasycom.com

FSC‐BT630 Datasheet Isense ‐ Current in SENSE STATE ‐ 100 ‐ nA Iactivated ‐ Current in ACTIVATED STATE ‐ 480 ‐ uA Rin_min ‐ Minimum input resistance when regulating voltage swing ‐ ‐ 40 Ω Rin_max ‐ Maximum input resistance when regulating voltage swing 1.0 ‐ ‐ kΩ Rin_loadmod ‐ Input resistance when load modulating 8 ‐ 22 Ω Imax ‐ Maximum input current on NFC pins ‐ ‐ 80 mA a: Input is high impedance in sense mode Table 22: NFCT Timing Parameters Parameter Min Typ Max Unit tactivate ‐ Time from task_ACTIVATE in SENSE or DISABLE state to ACTIVATE_A ‐ ‐ 500 uS or IDLE stateb tsense ‐ Time from remote field is present in SENSE mode to FIELDDETECTED ‐ ‐ 20 uS event is asserted b: Does not account for voltage supply and oscillator startup times 5.12 Power consumptions Table 23: Power consumptions (TBD) Parameter Test Conditions Type Unit TX & RX peak current in TX (0 dBm) ~5.3 mA peak current in TX (4 dBm) ~6.6 paeak current in RX ~5.4 NFC antenna pin current INFC1/2 80 mA Current consumption, sleep IOFF ‐ System OFF current, no RAM retention 0.3 uA ION ‐ System ON base current, no RAM retention 1.2 uA IRAM ‐ Additional RAM retention current per 4 KB 20 nA RAM section Power fail comparator IPOF ‐ Current consumption when enabled <4 uA Shenzhen Feasycom Technology Co., Ltd ‐27‐ www.feasycom.com

FSC‐BT630 Datasheet 6. MSL & ESD Table 24: MSL and ESD Parameter Value MSL (moisture sensitivity level) MSL 1 ESD HBM (human body model): 2KV ESD grade: ESD HBM (human body model): 500V 7. RECOMMENDED TEMPERATURE REFLOW PROFILE Prior to any reflow, it is important to ensure the modules were packaged to prevent moisture absorption. New packages contain desiccate (to absorb moisture) and a humidity indicator card to display the level maintained during storage and shipment. If directed to bake units on the card, please check the below Table 25 and follow instructions specified by IPC/JEDEC J‐STD‐033. Note: The shipping tray cannot be heated above 65°C. If baking is required at the higher temperatures displayed in the below Table 25, the modules must be removed from the shipping tray. Any modules not manufactured before exceeding their floor life should be re‐packaged with fresh desiccate and a new humidity indicator card. Floor life for MSL (Moisture Sensitivity Level) 3 devices is 168 hours in ambient environment 30°C/60%RH. Table 25: Recommended baking times and temperatures 125°C Baking Temp. 90°C/≤ 5%RH Baking Temp. 40°C/ ≤ 5%RH Baking Temp. Saturated @ Floor Life Limit Saturated @ Floor Life Limit Saturated @ Floor Life Limit MSL 30°C/85% + 72 hours @ 30°C/85% + 72 hours @ 30°C/85% + 72 hours @ 30°C/60% 30°C/60% 30°C/60% 3 9 hours 7 hours 33 hours 23 hours 13 days 9 days Feasycom surface mount modules are designed to be easily manufactured, including reflow soldering to a PCB. Ultimately it is the responsibility of the customer to choose the appropriate solder paste and to ensure oven temperatures during reflow meet the requirements of the solder paste. Feasycom surface mount modules conform to J‐STD‐020D1 standards for reflow temperatures. The soldering profile depends on various parameters necessitating a set up for each application. The data here is given only for guidance on solder reflow. Shenzhen Feasycom Technology Co., Ltd ‐28‐ www.feasycom.com

FSC‐BT630 Datasheet Typical Lead‐free Re‐flow Pre‐heat zone (A) — This zone raises the temperature at a controlled rate, typically 0.5 – 2 C/s. The purpose of this zone is to preheat the PCB board and components to 120 ~ 150 C. This stage is required to distribute the heat uniformly to the PCB board and completely remove solvent to reduce the heat shock to components. Equilibrium Zone 1 (B) — In this stage the flux becomes soft and uniformly encapsulates solder particles and spread over PCB board, preventing them from being re‐oxidized. Also with elevation of temperature and liquefaction of flux, each activator and rosin get activated and start eliminating oxide film formed on the surface of each solder particle and PCB board. The temperature is recommended to be 150 to 210 for 60 to 120 second for this zone. Equilibrium Zone 2 (C) (optional) — In order to resolve the upright component issue, it is recommended to keep the temperature in 210 – 217  for about 20 to 30 second. Reflow Zone (D) — The profile in the figure is designed for Sn/Ag3.0/Cu0.5. It can be a reference for other lead‐free solder. The peak temperature should be high enough to achieve good wetting but not so high as to cause component discoloration or damage. Excessive soldering time can lead to intermetallic growth which can result in a brittle joint. The recommended peak temperature (Tp) is 230 ~ 250 C. The soldering time should be 30 to 90 second when the temperature is above 217 C. Cooling Zone (E) — The cooling ate should be fast, to keep the solder grains small which will give a longer‐lasting joint. Typical cooling rate should be 4 C. Shenzhen Feasycom Technology Co., Ltd ‐29‐ www.feasycom.com

FSC‐BT630 Datasheet 8. MECHANICAL DETAILS 8.1 Mechanical Details  Dimension: 10mm(W) x 11.9mm(L) x 1.7mm(H) Tolerance: ±0.1mm  Module size: 10mm X 11.9mm Tolerance: ±0.1mm  Pad size: 0.9mmX0.6mm Tolerance: ±0.1mm  Pad pitch: 1.1mm Tolerance: ±0.1mm 9. HARDWARE INTEGRATION SUGGESTIONS 9.1 Soldering Recommendations FSC‐BT630 is compatible with industrial standard reflow profile for Pb‐free solders. The reflow profile used is dependent on the thermal mass of the entire populated PCB, heat transfer efficiency of the oven and particular type of solder paste used. Consult the datasheet of particular solder paste for profile configurations. Feasycom will give following recommendations for soldering the module to ensure reliable solder joint and operation of the module after soldering. Since the profile used is process and layout dependent, the optimum profile should be studied case by case. Thus following recommendation should be taken as a starting point guide. 9.2 Layout Guidelines(Internal Antenna) It is strongly recommended to use good layout practices to ensure proper operation of the module. Placing copper or any metal near antenna deteriorates its operation by having effect on the matching properties. Metal shield around the antenna will prevent the radiation and thus metal case should not be used with the module. Use grounding vias separated max 3 mm apart at the edge of grounding areas to prevent RF penetrating inside the PCB and causing an unintentional resonator. Use GND vias all around the PCB edges. The mother board should have no bare conductors or vias in this restricted area, because it is not covered by stop mask print. Also no copper (planes, traces or vias) are allowed in this area, because of mismatching the on‐board antenna. Following recommendations helps to avoid EMC problems arising in the design. Note that each design is unique and the following list do not consider all basic design rules such as avoiding capacitive coupling between signal lines. Following list is aimed to avoid EMC problems caused by RF part of the module. Use good consideration to avoid problems arising from digital signals in the design. Ensure that signal lines have return paths as short as possible. For example if a signal goes to an inner layer through a via, always use ground vias around it. Locate them tightly and symmetrically around the signal vias. Routing of any sensitive signals should be done in the inner layers of the PCB. Sensitive traces should have a ground area above and under the line. If this is not possible, make sure that the return path is short by other means (for example using a ground line next to the signal line). Shenzhen Feasycom Technology Co., Ltd ‐30‐ www.feasycom.com

FSC‐BT630 Datasheet 9.3 Layout Guidelines(External Antenna) Placement and PCB layout are critical to optimize the performances of a module without on‐board antenna designs. The trace from the antenna port of the module to an external antenna should be 50 and must be as short as possible to avoid any interference into the transceiver of the module. The location of the external antenna and RF‐IN port of the module should be kept away from any noise sources and digital traces. A matching network might be needed in between the external antenna and RF‐IN port to better match the impedance to minimize the return loss. As indicated in Figure 46 below, RF critical circuits of the module should be clearly separated from any digital circuits on the system board. All RF circuits in the module are close to the antenna port. The module, then, should be placed in this way that module digital part towards your digital section of the system PCB. 9.3.1 Antenna Connection and Grounding Plane Design General design recommendations are: The length of the trace or connection line should be kept as short as possible. Distance between connection and ground area on the top layer should at least be as large as the dielectric thickness. Routing the RF close to digital sections of the system board should be avoided. To reduce signal reflections, sharp angles in the routing of the micro strip line should be avoided. Chamfers or fillets are preferred for rectangular routing; 45‐degree routing is preferred over Manhattan style 90‐degree routing. Routing of the RF‐connection underneath the module should be avoided. The distance of the micro strip line to the ground plane on the bottom side of the receiver is very small and has huge tolerances. Therefore, the impedance of this part of the trace cannot be controlled. Use as many vias as possible to connect the ground planes. 10. PRODUCT PACKAGING INFORMATION 10.1 Default Packing a, Tray vacuum b, Tray Dimension: 180mm * 195mm Shenzhen Feasycom Technology Co., Ltd ‐31‐ www.feasycom.com

FSC‐BT630 Datasheet Figure 49: Tray vacuum (Image for reference only, subject to actual product) Shenzhen Feasycom Technology Co., Ltd ‐32‐ www.feasycom.com

FSC‐BT630 Datasheet FCC Statement 15.19 1. This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference. (2) This device must accept any interference received, including interference that may cause undesired operation. 15.21 Note: The grantee is not responsible for any changes or modifications not expressly approved by the party responsible for compliance. Such modifications could void the user’s authority to operate the equipment. 15.105(b) NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: ‐ Reorient or relocate the receiving antenna. ‐ Increase the separation between the equipment and receiver. ‐Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. ‐Consult the dealer or an experienced radio/TV technician for help RF Exposure Statement This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance of 20 cm between the radiator and your body. Instructions to the OEM/Integrator: This module has been granted modular approval for mobile applications. OEM integrators for host products may use the module in their final products without additional FCC/ISED (Innovation, Science and Economic Development Canada) certification if they meet the following conditions. Otherwise, Additional FCC/IC approvals must be obtained. ⚫ The OEM must comply with the FCC labeling requirements. If the module’s label is not visible when installed, then an additional permanent label must be applied on the outside of the finished product which states: ”Contains transmitter module FCC ID: 2AMWOFSC‐BT630”. Additionally, the following statement should be included on the label and in the final product’s user manual: “This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interferences, and (2) this device must accept any interference received, including interference that may cause undesired operation.” ⚫ The user’s manual for the host product must clearly indicate the operating requirements and conditions that must be Shenzhen Feasycom Technology Co., Ltd ‐33‐ www.feasycom.com

FSC‐BT630 Datasheet observed to ensure compliance with current FCC / IC RF exposure guidelines. ⚫ The final host / module combination may also need to be evaluated against the FCC Part 15B criteria for unintentional radiators in order to be properly authorized for operation as a Part 15 digital device. ⚫ This Module is full modular approval, it is limited to OEM installation ONLY. ⚫ The module is limited to installation in mobile application. ⚫ A separate approval is required for all other operating configurations, including portable configurations with respect to Part 2.1093 and difference antenna configurations. ⚫ The OEM integrator is responsible for ensuring that the end‐user has no manual instruction to remove or install module. ⚫ The Grantee will provide guidance to the Host Manufacturer for compliance with the Part 15B requirements if requested. Shenzhen Feasycom Technology Co., Ltd ‐34‐ www.feasycom.com


Document Created: 2019-04-16 16:38:39
Document Modified: 2019-04-16 16:38:39
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