Data Sheet

FCC ID: VO8-Q5

Operational Description

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FCCID_2536234

Preliminary Datasheet IS2020S Bluetooth 4.1 Multimedia SOC GENERAL DESCRIPTION IS2020S is a compact, highly integrated, FEATURES CMOS single-chip RF and baseband IC for  Support preliminary Bluetooth v4.1 preliminary Bluetooth v4.1 with Enhanced function and backward compatible with Data Rate 2.4GHz applications. This chip is BT3.0, 2.0 and 1.2. fully compliant with Bluetooth specification  ISSC’s own Bluetooth software stack for L and completely backward-compatible with the headset or speaker application. It Bluetooth 3.0, 2.0 or 1.2 systems. supports following profiles : A It incorporates Bluetooth 1M/2M/3Mbps - Hands Free 1.6 RF, single-cycle MCU, MODEM, UART - Headset 1.1 TI interface, and ISSC’s own Bluetooth software - A2DP 1.2 stack to achieve the required BT v4.1 with - AVRCP 1.5 EDR functions. EN - SPP 1.0 To provide the superior audio and voice  Integrated 16/32 bits DSP core running up quality, it also integrates a DSP co-processor, a to 72MHz that supports: PLL, and a CODEC dedicated for voice and - Dual microphone noise suppression - Echo cancelation D audio applications. For voice, not only the basic CVSD - SBC/AAC_LC audio format decoding - Automatic volume control for speaker FI encoding and decoding but also the enhanced noise reduction and echo cancellation are output  Integrated a 20-bit 98dB SNR implemented by the built-in DSP to reach the N ( A-weighted) stereo DAC better quality in the both sending and receiving  Connections to two phones with sides. For enhanced audio applications, SBC HFP/A2DP profiles O and AAC (optional) decoding functions can be  Built-in four languages ( Chinese/ also carried out by DSP to satisfy Bluetooth English/ Spanish/ French) voice prompts C A2DP requirements.  Ultra low power consumption under In addition, to minimize the external 10mA for SCO/A2DP link components required for portable devices, a  Capable charging voltage from an empty SC voltage sensor for battery, battery charger, a battery and sustain a direct DC input switching regulator and LDO are integrated to voltage up to 7V reduce BOM cost for various Bluetooth  Charging current up to 350mA applications.  7 mm x 7 mm 56 QFN package IS APPLICATIONS  Bluetooth stereo headset  Bluetooth stereo speaker  Bluetooth stereo speaker phone  Bluetooth car audio unit Phone: 886-3-577-8385 Website: www.issc-tech.com Draft 0.9 Mar 10, 2014

Preliminary Datasheet IS2020S Bluetooth 4.1 Multimedia SOC Table of Contents 1 KEY FEATURES ................................................................................................................................... 3 L 2 PIN ASSIGNMENTS .............................................................................................................................. 6 A 3 TRANSCEIVER ................................................................................................................................... 10 4 MICROPROCESSOR .......................................................................................................................... 11 TI 5 AUDIO .................................................................................................................................................. 12 EN 6 POWER MANAGE UNIT ..................................................................................................................... 13 7 GENERAL PURPOSE IOS .................................................................................................................. 15 8 SPECIFICATIONS ............................................................................................................................... 16 D 9 PACKAGE ........................................................................................................................................... 28 FI N O C SC IS Phone: 886-3-577-8385 Website: www.issc-tech.com Draft 0.9 Mar 10, 2014

Preliminary Data Sheet IS2020S 1 Key Features System Specification  Compliant with Bluetooth Specification v.4.1 (EDR) in 2.4 GHz ISM band Baseband Hardware L  16MHz main clock input A  Built-in internal ROM for program memory TI  Support to connect to two hosts ( phones, tablets…) with HFP or A2DP profiles simultaneously   EN Adaptive Frequency Hopping (AFH) avoids occupied RF channels Fast Connection supported D RF Hardware FI  Fully Bluetooth 4.1 (EDR) system in 2.4 GHz ISM band.  N Combined TX/RX RF terminal simplifies external matching and reduces external antenna switches. O  Max. +4dBm output power with 20 dB level control from register control. C  Built-in T/R switch for Class 2/3 application SC  To avoid temperature variation, temperature sensor with temperature calibration is utilized into bias current and gain control.  IS Fully integrated synthesizer has been created. There requires no external VCO, varactor diode, resonator and loop filter.  Crystal oscillation with built-in digital trimming for temperature/process variations. Audio processor  Support 64 kb/s A-Law or -Law PCM format, or CVSD (Continuous Variable Slope Delta Modulation) for SCO channel operation. -3-

Preliminary Data Sheet IS2020S  Noise suppression for dual analog microphone inputs  Echo cancelation  SBC and optional AAC decoding  Packet loss concealment L  Build-in four languages (Chinese/ English/ Spanish/ French) voice prompts and 20 A events for each one TI Audio Codec  EN 20 bit codec  98dB SNR DAC playback  Dual microphone input D  Integrate headphone amplifier for 16/32Ω speakers FI Peripherals N  Built-in Lithium-ion battery charger O  Integrate 3V, 1.8V LDO and Switching mode regulator C  Built-in ADC for battery monitor and voltage sense.  Two LED drivers SC Flexible HCI interface  High speed HCI-UART (Universal Asynchronous Receiver Transmitter) interface IS Package  7x7mm2 56QFN package -4-

Preliminary Data Sheet IS2020S Functional Diagram Clock PLL BT BDR/EDR L MCU Radio transceiver A TI PMU EEPROM RAM/ROM EN DSP CODEC D FI N O C SC IS -5-

Preliminary Data Sheet IS2020S 2 PIN ASSIGNMENTS L A TI EN D FI N O C SC IS -6-

ISSC 15SC Technologies Corp. Preliminary Data Sheet 1520208 Pin No. vO Pin Name Pin Descriptions 1 P VCOM IInternal biasing voltage for CODEC 2 I MICN2 IMic 2 mono differential analog negative input 3 I MICP2 IMic 2 mono differential analog positive input 4 I MICN1 IMic 1 mono differential analog negative input 5 I MICPI IMic 1 mono differential analog positive input 6 P MIC_BIAS |Electric microphone biasing voltage 7 I AR IR—channel single—ended analog inputs 8 I ATL IL—channel single—ended analog inputs 9 P VDD_CORE [Core 1.2V power input (GPTO, default pull—high input 10 to P12 1. KEY PIN for FT Test 2. EEPROM clock SCL 3. Clock signal for OLED (GPTO, default pull—high input 1. KEY PIN for FT Test U O PL3 2. EEPROM data SDA 3. Data signal for OLED [KEY PIN for FT Test 12 I RST_N . System Reset Pin 13 P VDD10 IVO power supply input (GPTO, default pull—high input 1. FWD key when class 2 RF 14 TO Po_1 2. Class1 TX Control signal of external TR switch when class 1 RF 3. Serial flash control. (GPTO, default pull—high input is to Pa L KEY PIN forv FT Tfest 2. System Configuration, L; Boot Mode with P2_0 low combination IGPTO, default pull—high input. 16 1O PO4 1. NFC detection pin 2. Out_Ind_0

ISSC 15SC Technologies Corp. Preliminary Data Sheet 1520208 Pin No. vO Pin Name Pin Descriptions (GPTO, default pull—high input 1. NEC detection pin 17 TO P1_5 2. Out_Ind_0 3. Slide Switch Detector. [KEY PIN for FT Test 18 1O HCLRXD HCT RX data [KEY PIN for FT Test 19 TO HCLTXD HCT TX data 20 P CODEC_VO [3.1V LDO output for CODEC power 21 P LDO31_VIN [3.1V LDO input 22 P LDO31_VO [3.1V LDO output 23 P ADAP_IN [Power adaptor input 24 P BAT_IN Battery input 25 P AMB_DET [ADC analog input1 26 P SAR_VDD JSAR 1.8V input 27 P SYS_PWR System Power Output 28 P BK_VDD Buck VDD Power Input 29 P BK_LX Buck feedback input 30 P BK_O Buck output 31 I PWR [Multi—Function Push Button key 32 I LED2 |LED Driver 2 33 I LED1 |LED Driver 1 (GPTO, default pull—high input 34 TO PO_0 1. Slide Switch Detector. 2. UART TX_IND (GPTO, default pull—high input L. REV key 2. Buzzer Signal Output 35 TO PO_3 3. Out_Ind_1 4. Class1 RX Control signal of external TR switch when class 1 RF 5. Serial flash control. 36 1 EAN |Embedded ROM/External Flash enable [H; Embedded; L; External Flash 1s.

199C 1820208 M Preliminary Data Sheet 15SC Technologies Corp. Pin No.| VO Pin Name Pin Descriptions 37 P CLDO_O JL2V core LDO output 38 P PMIC_IN IPMU blocks power input. 39 P RFLDO_O [L.28V RF LDO output 40 P VBG Bandgap output reference for decoupling interference 41 P ULPC_VSUS JULPC 1.2V output power, maximum loading ImA. 42 I xON 16MHz Crystal input negative 43 I xOP 16MHz Crystal input positive 44 RP VCC_RF IRF power input for both synthesizer and TX/RX block 45 TO RIX [RF RTX path 46 to Po2 (GPTO, default pull—high input v |Play/Pause key as the default setting (GPTO, default pull—high input 1. KEY PIN for FT Test 47 TO P20 v ; ho 2. System Configuration, H: Application L: Baseband(IBDK Mode) a3 to P27 (GPTO, default pull—high input |Volume up key (default) 49 to P30 GPIQ, default pull—high input [Line—in Detector (GPTO, default pull—high input 50 O P05 |Volume down (defaul) 51 P YDD10 IVO power supply input 52 0 AOHPR IR—channel analog headphone output 53 P VDDAO |Positive power supply dedicated to CODEC output amplifiers. 54 0 AOHPM (Headphone common mode output/sense input. 55 0 AOHPL IL—channel analog headphone output 56 P VDDA |Positive power supply/reference voltagefor CODEC 57 P EP lExposed pad as ground

Preliminary Data Sheet IS2020S 3 TRANSCEIVER IS2020S is design optimized for use in Bluetooth 2.4 GHz system. It contains a complete radio frequency transmitter/receiver section. An internal synthesizer generates a stable clock for synchronize with another device. TRANSMITTER L The internal PA has a maximum output power of +4dBm with level control 20dB from A amplitude control. This is applied into Class2/3 radios without external RF PA. The transmitter features IQ direct conversion to minimize the frequency drift. And it can TI excess 30dB power range with temperature compensation machine. EN RECEVIER The LNA operates with TR-combined mode for single port application. The ADC is utilized to sample input analogue wave to convert into digital for de-modulator analysis. Before the ADC, a channel filter has been integrated into receiver channel that can reduce D the external component count and increase the anti-interference capability. The image rejection filter is to reject image frequency for low-IF architecture. This filter for FI low-IF architecture is implied to reduce external BPF component for super heterodyne architecture. There is an RSSI signal to the processor that it can control the power to make a good tradeoff N for effective distance and current consumption. O SYNTHESIZER C A synthesizer generates a clock for radio transceiver operation. There is a VCO inside with tunable internal LC tank. It can reduce variation for components. A crystal oscillation with internal digital trimming circuit provides a stable clock for synthesizer. SC MODEM On the Bluetooth v1.2 specification and below, 1 Mbps was the standard data rate based on IS Gaussian Frequency Shift Keying (GFSK) modulation scheme. This basic rate modem meets BDR requirements of Bluetooth v2.0 with EDR specification. On the Bluetooth v2.0 with EDR specification, Enhanced Data Rate (EDR) has been introduced to provide 2 and 3 Mbps data rates as well as 1 Mbps. This enhanced data rate modem meets EDR requirements of Bluetooth v2.0 with EDR specification. For the viewpoint of baseband, both BDR and EDR utilize the same 1MHz symbol rate and 1.6 KHz slot rate. For BDR, 1 symbol represents 1 bit. However each symbol in the payload part of EDR packets represents 2 or 3 bits. This is achieved by using two different modulations, π/4 DQPSK and 8DPSK. - 10 -

Preliminary Data Sheet IS2020S 4 MICROPROCESSOR A single-cycle 8-bit MCU is inside IS2020S to carry out the required Bluetooth protocols. It can run at the range from 16MHz to a higher clock so that MCU firmware can dynamically consider the tradeoff between computing power and power consumption. MCU firmware is implemented in ROM (Read-Only-Memory) to minimize the power consumption of program execution and to save the cost of external flash. L MEMORY A A single-port synchronous interface is provided to memory. There are enough ROM and TI RAM to fulfill the requirement of processor. In addition, attached to the embedded processor bus are a register bank, a dedicated single-port memory, and flash memory. The processor coordinates all link control procedures and data movement using a set of pointer registers. EXTERNAL RESET EN A watchdog timer capable of reset the chip. It has an integrated Power-On Reset (POR) D circuit that resets all circuits to a known power-on state. This action can also be driven by an external reset signal that can be used to externally control the device, forcing it into a power-on FI reset state. The RST signal input is active low and no connection is required in most applications. N REFERENCE CLOCK IS2020S is composed of an integrated crystal oscillation function. It used a 16 MHz external O crystal and two specified load capacitors that a high quality system reference timer source is obtained. This feature is typically used to remove the initial tolerance frequency errors associated C with the crystal and its equivalent load capacitance in mass production. Frequency trim is achieved by adjusting the crystal load capacitance through on-chip trim capacitors Ctrim integrated in chip. The value of trimming capacitance is around 200fF per LSB at 5 bits word, therefore the SC overall adjustable clock frequency is around 40 KHz. Ctrim =200fF * (1~31) IS - 11 -

Preliminary Data Sheet IS2020S 5 AUDIO There are several stages for input and output that all can be programmed for varying gain response characteristics. At the microphone input side, you may use single-end input or differential input. One critical point in maintaining a high quality signal is to provide a stable bias voltage source for the condenser microphone’s FET. DC blocking capacitors may be used at both positive and negative sides of input. Internally, this analog signal is converted to 16-bit 8 kHz linear L PCM data. The voice data taken from common memory is converted to an analogue value by a DAC. A A multistage amplifier drives the audio signal and provides a differential signal between Line_out+ and Line_out-. The output amplifier is capable of driving a speaker directly if its impedance is TI 16/32Ω. DIGITAL SIGNAL PROCESSOR EN A digital signal processor (DSP) cooperates with MCU to deal with audio section. It provides audio processing with some advanced features. The DSP includes the capability to cancel the acoustic echo that may be present in a headset or speaker. All processing is performed by a DSP D with low power consumption. This technique will most effectively cancel the incoming echo signal without impact to the desired voice signal. An outgoing signal to the speaker which level FI exceeds a certain threshold (and therefore deemed likely to create echo) will result in suppression of signal along the input path from the microphone. Filtering is also applied and provides for a smoother transition for a more natural user experience. N DUAL MICROPHONE NOISE REDUCTION O This noise reduction technology virtually eliminates distracting background noise, including C crowds, wind, vehicles and other interruptions to your conversations. It support dual microphone inputs that one for main vocal input and the other for background noise. Of course, it can use only main vocal input for single microphone application. SC CODEC This built-in codec contains a high Signal/Noise performance. This built-in codec contains a analog to digital converter (ADC), a digital to analog converter (DAC) and additional analog IS circuitry. Signal to noise ratio (SNR) is the supreme facts of a CODEC. It provides a very low noise level for background white noise. The main music stream and vocal become clear with this low noise level. - 12 -

Preliminary Data Sheet IS2020S 6 POWER MANAGE UNIT The PMU inside the chip has two main features, charging a Li-ion battery and some regulators for voltage translation. A power switch is used to switch over the power source between battery and adaptor automatically. It also provides two LED drivers. CHARGING A BATTERY L IS2020S includes a built-in battery charger optimized for use with lithium polymer batteries. A The charger features a current sensor for charging control, user programmable current regulation and high accuracy voltage regulation. TI The charging current is configured in the EEPROM. Whenever the adaptor is plug-in, charging circuit is active. Reviving, Pre-charging, Constant Current and Constant Voltage modes are implemented and re-charging function is also included. The maximum charging current is EN 350mA. Charging curve Reviving Recharge Pre charge D CV Voltage 4.2v Mode Constant Current Mode Constant Voltage Mode Mode Mode Recharge Voltage FI 4.1v CC current 0.5c N CC Voltage 3.0v O Recharge current 0.25c C Precharge Voltage 2.5v Precharge Current 0.1c SC Reviving Current 2mA VOLTAGE MONITING IS A 10-bit Successive-Approximation-Register analog to digital converter (SAR ADC) provides one dedicated channel for battery voltage level detection. The warning level is programmable and stored in the EEPROM. This ADC provides a good resolution that MCU can control the charging process. VOLTAGE REGULATION The built-in voltage converter is used to convert the battery or adaptor power for power supply. It also integrates hardware architecture to control power on/off procedure. The built-in programmable LDOs provide power for codec and digital IO pads. It is used to buffer the high - 13 -

Preliminary Data Sheet IS2020S input voltage from battery or adapter. This LDO need s 1uF bypass capacitor. SWITCHING REGULATOR There is a bulk voltage convert generating the voltage for RF and baseband core power. This converter has good conversion efficiency to save power and fast transient response. L LED DRIVER A There are two dedicate LED drivers to control the LEDs. They provide enough sink current that LED can be connected directly with IS2020S. TI EN D FI N O C SC IS - 14 -

Preliminary Data Sheet IS2020S 7 GENERAL PURPOSE IOs IS2020S provides six general purpose IOs for keys setting and saved in the EEPROM. The first button must be power key. The power on/off functions only can be set on MFB pin. There are four different operations for every button. They are short click, long click, double click and combinations. L A GPIOs for Buttons Button Name Default Functions GPIO name Pin TI Button 0 Power / MFB MFB 27 Button 1 Volume UP P2_7 42 EN Button 2 Volume DN P0_5 43 Button 3 PLAY/PAUSE P0_2 40 Button 4 REV P0_3 30 D Button 5 FWD P0_1 12 FI Some signals were generated to indicate or control outside devices. The most popular applications are NFC for easy pairing, external audio amplifier for louder speaker and buzzer for N indication. O GPIOs for added functions C Functions GPIO configurable features Pins Slide switch P0_0 44 Buzzer P0_4 / P2_0 / P0_3 45 / 41 / 30 SC NFC detect P0_4 / P1_5 45 / 13 External AMP enable P1_6 / P1_5 33 / 13 IS - 15 -

Preliminary Data Sheet IS2020S 8 SPECIFICATIONS Table 1: Absolute Maximum Voltages Symbol Parameter Min Max Unit VDD_CORE Digital core supply voltage 1.14 1.26 V AVDD_PLL PLL supply voltage VCC_RF RF supply voltage 1.28 V L AVDD_SAR SAR ADC supply voltage 1.62 1.98 V VDD_AUDIO CODEC supply voltage 2.7 3.0 V A VDD_IO I/O supply voltage 3.6 V BK_VDD BUCK supply voltage 4.5 V TI 3V1_VIN Supply voltage 4.5 V BAT_IN Input voltage for battery 3.0 4.5 V ADP_IN Input voltage for adaptor 4.5 7.0 V EN TSTORE Storage temperature -40 +85 ºC Table 2: Recommended operate condition D Symbol Parameter Min Typical Max Unit VDD_CORE Digital core supply voltage 1.14 1.2 1.26 V FI AVDD_PLL PLL supply voltage VCC_RF RF supply voltage 1.28 V N AVDD_SAR SAR ADC supply voltage 1.62 1.8 1.98 V VDD_AUDIO CODEC supply voltage 2.7 2.7 3.0 V VDD_IO I/O supply voltage 2.7 3.0 3.3 V O BK_VDD BUCK supply voltage 3 4.5 V 3V1_VIN Supply voltage 3 4.5 V C BAT_IN Input voltage for battery 3 4.2 V ADP_IN Input voltage for adaptor 4.5 7 V TSTORE Storage temperature -10 +25 +60 ºC SC IS - 16 -

Preliminary Data Sheet IS2020S Table 3: BUCK switching regulator Parameter Min Typical Max Unit Input Voltage 3.0 3.8 4.5 V Output Voltage (Iload=70mA, Vin=4V) 1.7 1.8 2.05 V Output Voltage Accuracy ±5% % mV Output Voltage Adjustable Step 50 L /Step A Output Adjustment Range -0.1 +0.25 V Output ripple 10 15 mVRMS TI Average Load Current (ILOAD) 120 mA Conversion efficiency (BAT=3.8V, Iload = 50mA) 88 % EN Switching frequency 800 KHz Quiescent Current 1000 μ A Output Current (peak) 200 mA D mV/ Load Regulation (Iload = 10 ~ 100mA) 1 FI mA 0.03 %/V Line Regulation (3.2V < Vin < 4.2V) N (30) (mV/V) Logic Low Voltage 0.4 V O EN threshold Logic High Voltage 1.62 V C EN current 10 nA Shutdown Current <1 μ A SC IS - 17 -

199C 1820208 Y Preliminary Data Sheet 15SC Technologies Corp. Table 4: Low Drop Regulation Parameter Min Typical Max Unit Input Voltage 3.0 4.5 V Vour conec 2.9 Output Voitage V Vour i0 1.8 Output Accuracy (Vin=3.7V, oan=100mA, 27°C) +5 % Output current (average) 100 mA Drop—out volt prout vorage 200 mVy {Isaa = maximum output current) Quiescent Current . 45 A {excluding l0ad, lisea < 1mA) Regulation Load ad Regulati 40 my {hoaa= OmA to 100mA) LineRegulati e Regia \o.n 7 10 mVV (Vout+0.3V<Vin<4.5V) Logic Low Voitage 0.4 V EN threshold T Logic High Voitage 1.62 V EN current 10 nA Shutdown Current <1 J A —18—

Preliminary Data Sheet IS2020S Table 5: Battery Charger Parameter Min Typical Max Unit Input Voltage 4.5 5.0 7.0 V Supply current to charger only 3 4.5 mA Battery trickle charge current 0.1C mA (BAT_IN < trickle charge voltage threshold) L Headroom > 0.7V Maximum Battery 170 200 240 mA A (ADAP_IN=5V) Fast Charge Current Headroom = 0.3V Note: ENX2=0 160 180 240 mA TI (ADAP_IN=4.5V) Headroom > 0.7V Maximum Battery 330 370 420 mA EN (ADAP_IN=5V) Fast Charge Current Headroom = 0.3V Note: ENX2=1 180 220 270 mA (ADAP_IN=4.5V) D Trickle Charge Voltage Threshold 3 V Float Voltage 4.158 4.2 4.242 V FI Battery Charge Termination Current, 10 % (% of Fast Charge Current) N Note: O (1) C is set in EEPROM (2) Headroom = VADAP_IN – VBAT C (3) ENX2 is not allowed to be enabled when VADAP_IN – VBAT > 2V Table 6: LED driver SC Parameter Min Typical Max Unit Supply Voltage 1.7 1.8 1.98 V Open-drain Voltage 5.1 V IS Open-drain Current 5.5 mA Intensity Control 16 step Current Step 0.35 mA Power Down Open-drain Current 1 μ A Shutdown Current 1 μ A - 19 -

ISSC 15SC Technologies Corp. Preliminary Data Sheet 1520208 Table 7: Audio codec — Digital to Analogue Converter T= 25°C, Vdd=3.0V, 1KHz sine wave input, Bandwidth = 20~20KHz Parameter (Condition) Min. Typ. Max. Unit Over—sampling rate 128 S Resolution 16 Bits Output Sample Rate 8 48 KHz Signal to Noise Ratio Note: 1 96 aB (SNR @cap—less mode) for 48kHz Signal to Noise Ratio Note: 1 o8 aB (SNR @single—end made) for 48KHz Digital Gain 54 4.85 dB Digital Gain Resolution 2~6 dB Analog Gain —28 3 dB Analog Gain Resolution 1 dB Output Voitage Full—scale Swing (AVDD=2.8V) 495 742.5 my rms Maximum Output Power (16 load) 34.5 mW Maximum Output Power (329 load) 17.2 mW Allowed Load (Resistive) 8 16 0.C. o THD+N (160— load) 0.05 % Signal to Noise Ratio (SNR @ 160 load) 96 dB Note: (1) fy=1KHz, BAV=20~20KHz, A—weighted, THD+N < 0.01%, OdBFS signal, Load=100KO —20 —

ISSC 15SC Technologies Corp. Preliminary Data Sheet 1520208 Table 8: Audio codec — Analogue to Digital Converter T= 25°C, Vdd=3.0V, 1KHz sine wave input, Bandwidth = 20~20KHz Parameter (Condition) Min. Typ. Max. Unit Resolution 16 Bits Output Sample Rate 8 48 KHz BKHz 88 . . . 16KHz 88 Signal to Noise Fl.at\o. Note: 1 32KHz s8 (SNR @MIC or Ling—in mode} 44.1KHz 87 48KHz 87 dB Digital Gain —54 4.85 dB Digital Gain Resolution 2~6 dB MIC Boost Gain 20 Analog Gain 60 dB Analog Gain Resolution 2.0 dB Input full—scale at maximum gain (differential) 4 m¥ ims Input full—scale at minimum gain (differential) 800 m¥ ims 30B bandwidth 20 KHz Microphone mode (input impedance) 6 10 KQ Microphone mode (input capacitance) 20 pF THD+N (microphone input) @30mVrms input 0.02 % Note: (1) fy=1KHz, BAV=20~20KHz, A—weighted, THD+N < 1%, 150mVpp input >

199C 1820208 Y Preliminary Data Sheet 15SC Technologies Corp. Table 9: Transmitter section for BDR . Bluetooth . Parameter Min Typ Max wl Unit specification Maximum RF transmit power 4.0 5.0 —6 to 4 dBm RF power variation over temperature range with +2.0 dB compensation disabled RF power control range 18 216 dB RF power range control resolution £0.5 dB 20d$ bandwidth for modulated go5 S KHz carrier ACP F= Fot2MHz 42 +40 £20 dBm F= FotB3MHz —49 —48 £40 dBm ’:00:62,;141 MHz F= Eyt>SMHz —57 —53 £40 dBm Ati.,, maximum modulation 150 165 140<Affang<175 KHz Afome« maximum modulation 120 140 2115 KHz Afsevglftavg 0.92 0.94 20.80 ICFT 4.5 8 10.5 +75 KHz Drift rate 3.3 5 7.0 $20 KHz/5 Ous Drift (single slot packet) 12 540 KHz 2"" harmonic content 42 <—30 dBm 3" harmonic content 45 <—30 dBm 2.

ISSC 15SC Technologies Corp. Preliminary Data Sheet 1520208 Table 10: Transmitter section for EDR Bluetooth Min Typ Max mel us Unit specification Relative transmit power —1.2 —4 to 1 dB 100 a| 2.5 5 10 for all blocks KHz freq. error w TT /4 DQPSK max I .I . initial freq. 2.5 5 75 for all blocks KHz carrier frequency stability eror 10 5+004 block freq. 5 10 75 for all blocks KHz error 100 a| 2.5 5 10 for all blocks KHz freq. error 100 1 BDPSK max carrier initial freq. 2.5 5 75 for all blocks KHz frequencystability error 10 5+004 block freq. 5 10 75 for all blocks KHz error Tt 4 DQPSK RMS DEVM 7 20 % modulation 99% DEVM PASS 30 % accuracy Peak DEVM 25 <35 % BDQPSK RMS DEVM 7 s13 % modulation 99% DEVM PASS 20 % accuracy Peak DEVM 20 s25 % F> <—52 5—40 dBm Fo+BMHz In—band spuri n— .ar! spurious Es Fo—3MHz < 53 <40 s dBm emissions po _ ~40 <40 B Eo—SMHz 6 Bm Note: Fo=2441MHz 5 _, —34 <20 dBm Fo—2MHz lilke —34 526 dBm

Preliminary Data Sheet IS2020S F0-1MHz F= -37 ≤-26 dBm F0+1MHz F= -34 ≤-20 dBm F0+2MHz F= L -46 ≤-40 dBm F0+3MHz A EDR differential phase encoding 100 ≥99 % TI EN D FI N O C SC IS - 24 -

Preliminary Data Sheet IS2020S Table 11: Receiver section for BDR Frequency Bluetooth Min Typ Max Unit (GHz) specification 2.402 -90 Sensitivity at 0.1% 2.441 -90 ≤-70 dBm BER 2.480 -89 L Maximum received signal at 0.1% 0 0 ≥-20 dBm A BER Continuous power 0.030–2.000 -7 -10 TI required to block 2.000-2.400 -10 -27 Bluetooth 2.500-3.000 -11 -27 EN reception (for input power of -67dBm dBm with 0.1% BER) 3.000-12.75 -7 -10 D measured at the unbalanced port of FI the balun C/I co-channel 6 ≤11 dB N F= -6 ≤0 dB F0+1MHz O F= -6.5 ≤0 dB F0-1MHz C F= Adjacent channel -36 ≤-30 dB F0+2MHz SC selectivity C/I F= -28 ≤-9 dB F0-2MHz Note: F0=2441MHz F= -31 ≤-20 dB IS F0-3MHz F= -48 ≤-40 dB F0+5MHz F = Fimage -28 ≤-9 dB Maximum level of intermodulation -37 ≥-39 dBm interferers Spurious output level N/A dBm/Hz - 25 -

Preliminary Data Sheet IS2020S Table 12: Receiver section for EDR Freq. Modula Bluetooth Min Typ Max Unit (GHz) tion specification π/4 2.402 -90 DQPSK π/4 2.441 -90 ≤-70 dBm L DQPSK Sensitivity at π/4 A 0.01% BER 2.480 -89 DQPSK TI 2.402 8DPSK -83 2.441 8DPSK -83 ≤-70 dBm EN 2.480 8DPSK -82 π/4 Maximum received signal at -10 ≥-20 DQPSK dBm 0.1% BER D 8DPSK -10 ≥-20 π/4 ≤13 FI 5 dB C/I co-channel at 0.1% BER DQPSK 8DPSK 5 ≤21 dB N π/4 F= -11 ≤0 dB DQPSK O F0+1MHz 8DPSK -5 ≤5 dB π/4 C F= -8 ≤0 dB DQPSK F0-1MHz 8DPSK -4 ≤5 dB SC Adjacent π/4 channel F= -38.5 ≤-30 dB DQPSK selectivity C/I F0+2MHz 8DPSK -33.5 ≤-25 dB IS π/4 Note: F= -29 ≤-7 dB DQPSK F0=2441MHz F0-2MHz 8DPSK -25 ≤0 dB π/4 F= -32.5 ≤-20 dB DQPSK F0-3MHz 8DPSK -27 ≤-13 dB F= π/4 -49.5 ≤-40 dB F0+5MHz DQPSK - 26 -

Preliminary Data Sheet IS2020S 8DPSK -43.5 ≤-33 dB π /4 -29 ≤-7 dB F = Fimage DQPSK 8DPSK -25 ≤0 dB L A TI EN D FI N O C SC IS - 27 -

Preliminary Data Sheet IS2020S 9 PACKAGE L A TI EN D FI N O C SC IS - 28 -


Document Created: 2014-04-01 14:45:53
Document Modified: 2014-04-01 14:45:53
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