Schematics

FCC ID: V7TW1800R

Schematics

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FCCID_1919453

5 4 3 2 1 TENDA D D C Product Name: W1800R && W80E C Common Product: N/A WIRELESS ROUTER B B A A TENDA Title W1800R & W80E Size Document Number Rev A3 Cover Page 0.1 Date: Thursday, January 03, 2013 Sheet 1 of 24 5 4 3 2 1

5 4 3 2 1 W80E/W1800R VIN 12V ,AND FB VDD12 CURRENT ABOUT 2.5A L1 CAP/0402_0 1 1 3 C115 C116 1 1 1 C114 C117 + + C118 TP23 TP24 TP25 J2 6 7 8 9 6 7 8 9 6 7 8 9 2 2 2 2 2 CAP/0402_0 1 2 6 7 8 9 6 7 8 9 6 7 8 9 C_0 5 5 5 JP3PIN 5 5 5 C_0 4 3 2 1 4 3 2 1 4 3 2 1 CAP_3 L4 4 3 2 1 4 3 2 1 4 3 2 1 D D TEST POINT_1 TEST POINT_1 TEST POINT_1 FB TP26 TP27 TP28 6 7 8 9 6 7 8 9 6 7 8 9 1 R28 C121 1 6 7 8 9 6 7 8 9 6 7 8 9 5 5 5 CAP C122 R29 C123 5 5 5 4 3 2 1 4 3 2 1 4 3 2 1 R_2 2 CAP CAP 4 3 2 1 4 3 2 1 4 3 2 1 R30 2 R_2 TEST POINT_1 TEST POINT_1 TEST POINT_1 7 1 U10 C124 VDD12 VDD5_5G EN BS L5 VDD5 CAP RES 2 3 L6 R31 VIN SW/VOUT 2.4GPA 7 1 U11 MAX CURRENT 1A FOR USB 2.0 *2VDD5_USB INDUCTOR IRON/SM_0 FB VDD5_2.4G VDD12 RES PGND/NC EN BS R32 L8 6 5 L7 SS/NC COMP/NC FB/NC 2 3 GND C131 VIN SW/VOUT R33 C3 +C12 +C133 C137 FB INDUCTOR IRON/SM_0 C2 C1 C127 C128 C129 C130 PGND/NC R35 1 1 1 1 R34 C138 C139 C141 C142 6 5 C136 C147 C144 C145 DCDC-RT8237-S08_0 4 9 8 RES SS/NC COMP/NC FB/NC GND CAP CAP RES CAP/0402_0 CAP NP_2 CAP/0402_0 CAP NP_2 C135 CAP C146 2 2 2 2 C150 C151 C152 C153 R36 CAP RES CAP C134 CAP- Polarity capacitance CAP CAP 4 9 8 CAP CAP- Polarity capacitance R37 CAP DCDC-RT8237-S08_0 RES CAP CAP RES CAP_9 RES CAP CAP C155 CAP CAP CAP CAP input capacitance >61.3uF Can change for tantalum capacitor CAP C154 CAP CAP_8 CAP VDD5_5G C C H10 1 2 J-CON2 VDD12 R38 2 1 VDD3_3 R39 R_2 3.3V C156 For 4706,4331,4360 RES 1 1 1 R40 VDD3_3 C159 CAP L9 (2604) C157 R41 C158 R_2 1 2 2 CAP Max Current 3A CAP NP_2 INDUCTOR IRON/SM_0 2 CAP NP_8 R_2 VDD1_8 2 R_3 L10 1 7 1 U13 D1 R42 VDD12 EN BS C9 INDUCTOR IRON/SM_0 5 4 D U12 VDD12 2 2 3 CAP- Polarity capacitance EN BS CAP CAP- Polarity capacitance SW 3 VIN SW/VOUT 2 SW CAP 1 R43 PGND/NC VIN 6 5 C8 + C170 + C160 C174 C175 SS/NC COMP/NC FB/NC C166 + C167 C176 C171 GND CAP CAP 7 6 C165 C11 C4 C172 C161 C173 VCC FB C5 C162 C163 C164 H3 H1 H2 GND R45 1 1 1 EG DCDC-RT8237-S08_0 4 9 8 RES 1 1 C169 C178 CAP R44 CAP CAP 1 1 1 R_3 MIC5209-3_0.3BS R46 C179 CAP CAP 9 8 B B CAP CAP 2 CAP- Polarity capacitance TEST POINT_0TEST POINT_0 TEST POINT_0 CAP CAP CAP NP_10 CAP 2 CAP CAP CAP R_0 RES CAP H4 H5 H6 1 1 1 CAP 1 1 1 TEST POINT_0TEST POINT_0 TEST POINT_0 H7 H8 H9 1 1 1 1 1 1 TEST POINT_0 TEST POINT_0 TEST POINT_0 VDD1_2_RF_5G VDD1_2_RF_2.4G VDD1_2 VDD3_3 1.2V For 4706 L11 1.2V For BCM4360 1.2V For BCM4331 L12 INDUCTOR IRON/SM_0 1 C180 FB R47 1 2 L13 VDD3_3 U14 VDD2_5 2.5V R_1 CAP NP_1 FB AME8805 For 4706 & 53125 1 3 R48 VIN VOUT 2 2 1 R49 M1 M2 M3 GND1 GND2 1 1 1 D2 R_1 R_0 1 1 1 1 1 CAP CAP 1 2 C10 C192 C193 C194 1 1 1 D C191 C185 5 4 CAP VDD12 C181 U15 TEST POINT_0 TEST POINT_0 TEST POINT_0 2 4 CAP CAP NP_1 CAP NP_1 CAP/0402_0 CAP NP_1 CAP NP_1 2 C182 C183 C184 C190 2 2 2 2 2 EN BS CAP CAP CAP NP_2 SW 3 M4 M5 M6 SW C7 + C189 +C195 C196 C197 1 1 1 CAP 1 CAP VIN LDO-AME8805 CAP- Polarity capacitance CAP-Polarity capacitance 1 1 1 A 7 6 TEST POINT_0 TEST POINT_0 TEST POINT_0 A C6 C198 C188 VCC FB GND R_1 2 EG C199 R50 MIC5209-3_0.3BS CAP 9 8 CAP CAP 1 CAP TENDA Title W1800R & W80E Size Document Number Rev A2 12 to 3.3/2.5/1.8 0.1 Date: Tuesday, February 19, 2013 Sheet 5 of 24 5 4 3 2 1

5 4 3 2 1 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 VDD1_8 VDD1_8 C69 C70 C71 C72 C73 C74 C75 C76 C77 C78 C79 C80 C81 C82 C83 C84 C85 C86 C87 C88 C89 C90 6.3V 6.3V Place these caps under the DDR2. Place these caps under the DDR2. VREF VREF U7 U8 M9 M9 G1 G3 G7 G9 G1 G3 G7 G9 R1 C1 C3 C7 C9 R1 C1 C3 C7 C9 SDRAM-DDR-64M16-FBGA84 SDRAM-DDR-64M16-FBGA84 A1 E1 A9 E9 A1 E1 A9 E9 J9 J1 J9 J1 D D BGA84_0.8mm C91 BGA84_0.8mm C92 CAP_4 VDD VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDL VDD VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDL CAP_4 DDR2_ADDR_0 M8 J2 DDR2_ADDR_0 M8 J2 DDR2_ADDR_1 M3 A0 VREF DDR2_ADDR_1 M3 A0 VREF DDR2_ADDR_2 M7 A1 DDR2_ADDR_2 M7 A1 DDR2_ADDR_3 N2 A2 G8 DDR2_DATA_0 DDR2_ADDR_3 N2 A2 G8 DDR2_DATA_16 DDR2_ADDR_4 N8 A3 DQ0 G2 DDR2_DATA_1 DDR2_ADDR_4 N8 A3 DQ0 G2 DDR2_DATA_17 DDR2_ADDR_5 N3 A4 A5 1Gb DQ1 DQ2 H7 DDR2_DATA_2 DDR2_ADDR_5 N3 A4 A5 1Gb DQ1 DQ2 H7 DDR2_DATA_18 DDR2_ADDR_6 N7 H3 DDR2_DATA_3 DDR2_ADDR_6 N7 H3 DDR2_DATA_19 DDR2_ADDR_7 P2 A6 A7 DDR2 SDRAM DQ3 DQ4 H1 DDR2_DATA_4 DDR2_ADDR_7 P2 A6 A7 DDR2 SDRAM DQ3 DQ4 H1 DDR2_DATA_20 DDR2_ADDR_8 P8 H9 DDR2_DATA_5 DDR2_ADDR_8 P8 H9 DDR2_DATA_21 DDR2_ADDR_9 P3 A8 A9 64Mx16 DQ5 DQ6 F1 DDR2_DATA_6 DDR2_ADDR_9 P3 A8 A9 64Mx16 DQ5 DQ6 F1 DDR2_DATA_22 DDR2_ADDR_10 M2 F9 DDR2_DATA_7 DDR2_ADDR_10 M2 F9 DDR2_DATA_23 DDR2_ADDR_11 P7 A10/AP NC = A2,E2 DQ7 C8 DDR2_DATA_8 DDR2_ADDR_11 P7 A10/AP NC = A2,E2 DQ7 C8 DDR2_DATA_24 DDR2_ADDR_12 R2 A11 DQ8 C2 DDR2_DATA_9 DDR2_ADDR_12 R2 A11 DQ8 C2 DDR2_DATA_25 DDR2_ADDR_13 R8 A12 DQ9 D7 DDR2_DATA_10 DDR2_ADDR_13 R8 A12 DQ9 D7 DDR2_DATA_26 DDR2_CLK0_P DDR2_ADDR_14 R3 A13/NC DQ10 D3 DDR2_DATA_11 DDR2_CLK2_P DDR2_ADDR_14 R3 A13/NC DQ10 D3 DDR2_DATA_27 R7 A14/NC DQ11 D1 DDR2_DATA_12 R7 A14/NC DQ11 D1 DDR2_DATA_28 A15/NC DQ12 A15/NC DQ12 1 1 RES_1 D9 DDR2_DATA_13 RES_1 D9 DDR2_DATA_29 R21 DDR2_BA_0 L2 DQ13 B1 DDR2_DATA_14 R22 DDR2_BA_0 L2 DQ13 B1 DDR2_DATA_30 DDR2_BA_1 L3 BA0 DQ14 B9 DDR2_DATA_15 DDR2_BA_1 L3 BA0 DQ14 B9 DDR2_DATA_31 1% DDR2_BA_2 L1 BA1 DQ15 1% DDR2_BA_2 L1 BA1 DQ15 C93 BA2 C94 BA2 2 2 J8 B7 DDR2_DQS_P_1 J8 B7 DDR2_DQS_P_3 K8 CK_P UDQS_P A8 DDR2_DQS_N_1 K8 CK_P UDQS_P A8 DDR2_DQS_N_3 CK_N UDQS_N CK_N UDQS_N 1 CAP_4 CAP_4 1 F7 DDR2_DQS_P_0 R24 F7 DDR2_DQS_P_2 R23 DDR2_CKE K2 LDQS_P E8 DDR2_DQS_N_0 DDR2_CKE K2 LDQS_P E8 DDR2_DQS_N_2 CKE LDQS_N 1% CKE LDQS_N 1% B3 DDR2_DQM_1 RES_1 B3 DDR2_DQM_3 2 RES_1 DDR2_CS_N L8 UDM F3 DDR2_DQM_0 DDR2_CS_N L8 UDM F3 DDR2_DQM_2 2 DDR2_CLK0_N CS LDM DDR2_CLK2_N CS LDM Place under the DDR2 DDR2_RAS_N K7 K9 DDR2_ODT Place under the DDR2 DDR2_RAS_N K7 K9 DDR2_ODT DDR2_CAS_N L7 RAS ODT DDR2_CAS_N L7 RAS ODT DDR2_WE_N K3 CAS DDR2_WE_N K3 CAS VSSDL VSSDL WE WE VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS C C A3 E3 J3 N1 P9 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 J7 A3 E3 J3 N1 P9 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 J7 VREF C95 U9E CAP_4 BCM4706KPBG_0 BGA484P06-10 AA4 Y3 DDR2_DATA_0 DDR_SDRAM_VREF DDR_SDRAM_DQ0 AA2 DDR2_DATA_1 DDR2_ADDR_0 Y7 DDR_SDRAM_DQ1 AA1 DDR2_DATA_2 DDR2_ADDR_1 AA7 DDR_SDRAM_ADDR0 DDR_SDRAM_DQ2 Y2 DDR2_DATA_3 DDR2_ADDR_2 AB6 DDR_SDRAM_ADDR1 DDR_SDRAM_DQ3 W3 DDR2_DATA_4 DDR2_ADDR_3 W7 DDR_SDRAM_ADDR2 DDR_SDRAM_DQ4 W2 DDR2_DATA_5 DDR2_ADDR_4 Y8 DDR_SDRAM_ADDR3 DDR_SDRAM_DQ5 W1 DDR2_DATA_6 DDR2_ADDR_5 AB7 DDR_SDRAM_ADDR4 DDR_SDRAM_DQ6 Y1 DDR2_DATA_7 DDR2_ADDR_6 Y9 DDR_SDRAM_ADDR5 DDR_SDRAM_DQ7 P4 DDR2_DATA_8 VDD1_8 DDR2_ADDR_7 AA9 DDR_SDRAM_ADDR6 DDR_SDRAM_DQ8 P2 DDR2_DATA_9 DDR2_ADDR_8 AB8 DDR_SDRAM_ADDR7 DDR_SDRAM_DQ9 R2 DDR2_DATA_10 DDR2_ADDR_9 W9 DDR_SDRAM_ADDR8 DDR_SDRAM_DQ10 R1 DDR2_DATA_11 DDR_SDRAM_ADDR9 DDR_SDRAM_DQ11 1 DDR2_ADDR_10 Y10 P1 DDR2_DATA_12 CAP_4 DDR2_ADDR_11 AB9 DDR_SDRAM_ADDR10 DDR_SDRAM_DQ12 N4 DDR2_DATA_13 R25 C96 DDR2_ADDR_12 W10 DDR_SDRAM_ADDR11 DDR_SDRAM_DQ13 M1 DDR2_DATA_14 RES_1 DDR2_ADDR_13 AB10 DDR_SDRAM_ADDR12 DDR_SDRAM_DQ14 M2 DDR2_DATA_15 1% VREF AA10 DDR_SDRAM_ADDR13 DDR_SDRAM_DQ15 K2 Place the VREF divider DDR2_ADDR_14 DDR2_DATA_16 2 DDR_SDRAM_ADDR14 DDR_SDRAM_DQ16 K4 DDR2_DATA_17 close to the 4706 DDR2_BA_0 AB5 DDR_SDRAM_DQ17 L2 DDR2_DATA_18 DDR_SDRAM_BA0 DDR_SDRAM_DQ18 1 DDR2_BA_1 Y6 L1 DDR2_DATA_19 DDR2_BA_2 AA5 DDR_SDRAM_BA1 DDR_SDRAM_DQ19 K1 DDR2_DATA_20 R26 C97 DDR_SDRAM_BA2 DDR_SDRAM_DQ20 H4 DDR2_DATA_21 RES_1 B DDR2_DQM_0 AA3 DDR_SDRAM_DQ21 E1 DDR2_DATA_22 1% CAP_4 B DDR2_DQM_1 R4 DDR_SDRAM_DM0 DDR_SDRAM_DQ22 E2 DDR2_DATA_23 2 DDR2_DQM_2 L4 DDR_SDRAM_DM1 DDR_SDRAM_DQ23 F1 DDR2_DATA_24 DDR2_DQM_3 F3 DDR_SDRAM_DM2 DDR_SDRAM_DQ24 F2 DDR2_DATA_25 DDR_SDRAM_DM3 DDR_SDRAM_DQ25 CAP_4 CAP_4 CAP_4 B1 DDR2_DATA_26 DDR2_DQS_P_0 U2 DDR_SDRAM_DQ26 E3 DDR2_DATA_27 DDR2_DQS_N_0 U1 DDR_SDRAM_DQSP0 DDR_SDRAM_DQ27 D1 DDR2_DATA_28 DDR_SDRAM_DQSN0 DDR_SDRAM_DQ28 D3 DDR2_DATA_29 DDR2_DQS_P_1 N1 DDR_SDRAM_DQ29 A2 DDR2_DATA_30 DDR2_DQS_N_1 N2 DDR_SDRAM_DQSP1 DDR_SDRAM_DQ30 A3 DDR2_DATA_31 DDR_SDRAM_DQSN1 DDR_SDRAM_DQ31 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 DDR2_DQS_P_2 H1 VDD1_8 DDR_SDRAM_DQSP2 CAP_4 DDR2_DQS_N_2 H2 DDR_SDRAM_DQSN2 A1 DDR2_DQS_P_3 C1 DDR_OVDD_1P8_1 C3 DDR2_DQS_N_3 C2 DDR_SDRAM_DQSP3 DDR_OVDD_1P8_2 G1 C98 C99 C100 C101 C102 C103 C104 C105 C106 C107 C108 C109 C110 C111 C112 C113 DDR_SDRAM_DQSN3 DDR_OVDD_1P8_3 G3 DDR2_CKE V4 DDR_OVDD_1P8_4 H8 6.3V DDR2_RAS_N V5 DDR_SDRAM_CKE DDR_OVDD_1P8_5 J3 DDR2_CAS_N W5 DDR_SDRAM_RAS DDR_OVDD_1P8_6 M3 DDR_SDRAM_CAS DDR_OVDD_1P8_7 DDR2_WE_N AB4 DDR_SDRAM_WE DDR_OVDD_1P8_8 M8 Pin G1 Pin G3 Pin H8 Pin J3 Pin M8 Pin P3 Pin R10 Pin V1 Pin V10 Pin W8 Pin Y4 Pin C3 Pin M3 Pin V6 DDR2_ODT AB3 DDR_SDRAM_ODT DDR_OVDD_1P8_9 P3 Pin A1 R10 DDR2_CS_N W6 DDR_OVDD_1P8_10 V1 DDR_SDRAM_CS_L DDR_OVDD_1P8_11 V6 DDR2_CLK0_P AB1 DDR_OVDD_1P8_12 V10 DDR2_CLK0_N AB2 DDR_SDRAM_CK0P DDR_OVDD_1P8_13 W8 DDR_SDRAM_CK0N DDR_OVDD_1P8_14 Y4 DDR2_CLK2_P J1 DDR_OVDD_1P8_15 DDR2_CLK2_N J2 DDR_SDRAM_CK2P W11 ZCOMP DDR_SDRAM_CK2N DDR_SDRAM_ZQ 1 R27 RES_1 1% 2 A A TENDA Title W1800R & W80E Size Document Number Rev C DDR 0.1 Date: Tuesday, February 19, 2013 Sheet 6 of 24 5 4 3 2 1

5 4 3 2 1 U9D VDD3_3 BCM4706KPBG_0 VDD3_3 4706 Strapping Function Setting Default BGA484P06-10 option pin Pull NFLASH_CLE E17 E10 NFLASH_D0 R51 FLASH_ADDR0/NFLASH_CLE FLASH_DATA0 CAP_4 NFLASH_ALE C17 D10 NFLASH_D1 FLASH_ADDR1/NFLASH_ALE FLASH_DATA1 U16 2 1 MIPS_ENDIAN FLASH_ADDR6 0 = Standard JTAG port [default] 0 PD NFLASH_WP_L A17 FLASH_ADDR2/NFLASH_WP FLASH_DATA2 B10 NFLASH_D2 C200 E16 A10 NFLASH_D3 SFLASH_SO 5 8 1 = MIPS EJTAG port D16 FLASH_ADDR3 FLASH_DATA3 D9 NFLASH_D4 VDD3_3 SFLASH_CLK 6 SI VCC RES_1 B16 FLASH_ADDR4 FLASH_DATA4 E9 NFLASH_D5 SFLASH_CS0_L 1 SCK 2 SFLASH_SI MIPS_EJTAG_MODE A16 FLASH_ADDR5 FLASH_DATA5 C9 NFLASH_D6 WP_L 3 CS# SO FLASH_ADDR19 Strapping Option: FLASH_ADDR8 0 = GMAC port voltage is 2.5V (for RGMII) [default] 0* PD D15 FLASH_ADDR6 FLASH_DATA6 A9 NFLASH_D7 1 2 7 WP# 4 Install jumper on J1 FLASH_ADDR7 FLASH_DATA7 HOLD#GND 1 = GMAC port voltage is 3.3V (for MII) E15 FLASH_ADDR8 FLASH_DATA8 E8 for Big Endian C15 D8 R52 MX25L6405DMI-12G_0 FLASH_ADDR9 FLASH_DATA9 VDD3_3 A15 B8 RES_0 FLASH_ADDR10 FLASH_DATA10 VDD3_3 E14 FLASH_ADDR11 FLASH_DATA11 A8 compatible 16M Flash R53 FLASH_ADDR12 0 = PCIe port #1 is enabled [default] 0* PD D14 FLASH_ADDR12 FLASH_DATA12 D7 1 2 GMAC_MODE_1 B14 E7 1 = PCIe port #1 is disabled for power savings. A14 FLASH_ADDR13 FLASH_DATA13 C7 RES_1 FLASH_ADDR14 FLASH_DATA14 D D13 A7 RES_1 D R59 FLASH_ADDR15 FLASH_DATA15 2 1 E13 FLASH_ADDR16 FLASH_ADDR16 0 = Use internal PLL to generate REFCLK 0* PD C13 FLASH_ADDR17 FLASH_CS0_L C18 SFLASH_CS0_L R54 SFLASH_BOOT A13 B6 NFLASH_CS_L VDD3_3 and output it [default] MIPS_ENDIAN E12 FLASH_ADDR18 FLASH_CS1_L 2 1 GMAC_MODE_0 1 = Use the external REFCLK input D12 FLASH_ADDR19 A18 NFLASH_RE_L U17 FLASH_ADDR20 FLASH_OE_L/NFLASH_RE_L M25P64 NFLASH_RDYBSY B12 B18 NFLASH_WE_L RES_1 TX_DELAY_MODE A12 FLASH_ADDR21/NFLASH_R/B FLASH_WE_L/NFLASH_WE_L FLASH_ADDR22 WP_L 1 16 SFLASH_CLK FLASH_ADDR17 If FLASH_ADDR18 (SFLASH_BOOT) is set to "0" then: 0* PD RX_DELAY_MODE D11 FLASH_ADDR23 2 HOLD SCK 15 SFLASH_SO FLASH_ADDR[25:24] Strapping Option: GMAC_MODE_0 E11 VCC SI 3 14 0 = 8-bit parallel flash [default] GMAC_MODE_1 C11 FLASH_ADDR24 A6 SFLASH_SO 4 NC1 NC5 13 Set RGMII mode. A11 FLASH_ADDR25 SFLASH_SO E6 SFLASH_SI 1 = 16-bit parallel flash FLASH_ADDR26 SFLASH_SI D6 SFLASH_CLK 5 NC2 NC6 12 6 NC3 NC7 11 SFLASH_CLK SFLASH_CS0_L 7 NC4 NC8 10 U57 If FLASH_ADDR18 (SFLASH_BOOT) is set to "1" then: SFLASH_SI 8 CS VSS 9 WP_L MT29F8G08ABABAWP-TSSOP48_0 SO WP TSOP48 0 = ST Micro serial flash [default] NAND FLASH 1 = Atmel serial flash 1Gx8 CAP CAP 8Gbit VDD3_3 NFLASH_D0 44 NFLASH_D1 43 DQ7 37 FLASH_ADDR18 0 = Boot from paralled flash [default] 1 PD NFLASH_D2 42 DQ6 VCC 12 1 = Boot from serial flash [setting] DQ5 VCC C898 C899 NFLASH_D3 41 VDD3_3 VDD3_3 DQ4 NFLASH_D4 32 R55 R56 NFLASH_D5 31 DQ3 47 NFLASH_D6 30 DQ2 NC19 46 FLASH_ADDR19 0 = Little Endian [default] 0 PD 2 1 MIPS_EJTAG_MODE 2 1 SFLASH_BOOT NFLASH_D7 29 DQ1 NC18 45 1 = Big Endian RES_1 DQ0 NC17 40 VDD3_3 NFLASH_WP_L 19 NC16 33 RES_1 NFLASH_CLE 16 WP NC15 28 Pin 12 Pin 37 FLASH_ADDR6 Strapping Option: FLASH_ADDR18 Strapping Option: NFLASH_ALE 17 CLE NC14 27 FLASH_ADDR22 0 = No delay on GMAC_TXCLK [default] 1 PD Load R12 for EJTAG mode. Set to boot from serial flash. ALE NC13 24 2 1 = 2ns delay on GMAC_TXCLK [setting] R299 10 NC12 23 NFLASH_CS_L 9 NC_CE2 NC11 22 VDD3_3 CE1 NC10 RES_0 21 VDD3_3 NC9 NFLASH_RE_L 8 20 FLASH_ADDR23 0 = No delay on GMAC_RXCLK [default] 1 PD R57 R58 NFLASH_WE_L 18 RE NC8 15 1 1 = 2ns delay on GMAC_RXCLK [setting] 2 1 TX_DELAY_MODE 2 1 RX_DELAY_MODE NFLASH_RDYBSY WE NC7 14 6 NC6 11 NC_R/B2 NC5 CAP CAP 7 5 VDD3_3 R/B1 NC4 RES_1 RES_1 4 C FLASH_ADDR[25:24] 00 = RvMII [default] 10 PD,PD 39 NC3 3 C 01 = MII mode FLASH_ADDR22 Strapping Option: FLASH_ADDR23 Strapping Option: 34 DNU/ONFI_VCCQ1 NC2 2 Set 2ns delay on GMAC_RXCLK. C896 C897 DNU/ONFI_VCCQ0 NC1 1X = RGMII [setting] Set 2ns delay on GMAC_TXCLK. 38 DNU3 NC0 1 35 26 DNU1 * = Strapping option set at the detfault with no option to change. 48 DNU0 36 25 DNU/ONFI_VSSQ1 VSS 13 DNU/ONFI_VSSQ0 VSS Pin 39 Pin 34 1) Completely remove all the components connected to the USB pins. 2) Connect all the pins on the left side of the above symbol to GROUND. 3) Leave all the pins on the right side of the above symbol floating. VDD5_USB Place close to the USB connectors. CAP_4 CAP_4 VDD3_3 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 VDD3_3 FB_0 FB26 CAP_4 FB1 VDD5_USB_1 R61 AVDD DVDD C211 RES C201 FB C227 C204 C205 C206 C207 C208 C209 C210 C212 C213 C214 2 1 R63 CAP_5 R-0603 CAP_4 OVCUR1 C215 2 1 R64 CAP_5 CAP_4 R-0603 Closed to the chip relative pin CAP_4 Closed to the chip relative pin B B VDD3_3 R65 1 2 PGANG R_1 U9I VDD3_3 gang model BCM4706KPBG_0 C218 VDD3_3 FB_0 BGA484P06-10 RREF 1 FB2 CAP_4 R67 USB_A_3P3 U19 T22 1 R66 2 USB_AVDD_3P3 USB_RREF RES_1 C216 C217 RES_1 300mA CAP_4 SKT-8-USB-2STACK-4SHLD-J_0 2 CAP_4 VDD5_USB_1 J3 VDD2_5 D20 USB_OC_L U18 RouteR68 1 these2 traces as a 90ohm differential FB3 USB_OCD GLI8024-48_0 1 USB_A_2P5 R20 pair. RES_1 USB_DM_1 2 UPPER USB_AVDD_2P5 USB_DP1 1 2 USB_DP_1 USB_DP_1 3 C219 FB_0 C220 U22 USB_DM0 AVDD 1 28 USB_DP1 L14 4 USB_DATA_M AVDD DP1 COM-MODE-CHOKE-14-23_16 300mA CAP_4 V22 USB_DP0 USB_DM2 2 27 USB_DM1 USB_DATA_P DM2 DM1 USB_DM1 4 3 USB_DM_1 CAP_4 R69USB_DP2 3 26 USB_DP0 RES_1 1 2 4 DP2 RREF GL850G DP0 DM0 25 USB_DM0 1 R70 2 5 VDD1_2 AVDD 5 24 AVDD RES_1 USB_DM_2 6 LOWER C221 FB4 6 AVDD X1 SSOP28 V33 V5 23 1 R71 2 USB_DP_2 7 1 USB_D_1P2 T19 7 22 8 USB_DVDD_1P2 X2 PWREN1# RES_1 3 Y1 8 21 OVCUR1 USB_DP2 1 2 USB_DP_2 C222FB_0 C223 C224 9 DM3 OVCUR1# 20 DP3 PWREN2# L15 300mA CAP_4 AVDD 10 19 VDD5_USB COM-MODE-CHOKE-14-23_16 9 2 CAP_4 T21 11 AVDD OVCUR2# 18 PGANG R73 USB_DM2 4 3 USB_DM_2 10 SHIELD U20 USB_AVSS_1 12 DM4 PGANG 17 1 2 11 R72 1 R74 2 D3 D5 PINS USB_AVSS_2 13 DP4 PSELF 16 DVDD 12 /RESET_L RESET# DVDD RES_1 VDD1_2 14 15 RES_1 CRYSTAL_0 TEST/SCL GND D4 D6 R75 C-0603 DIO-TVS-BIPOLAR DIO-TVS-BIPOLAR 1 2 USB_AVDD1P2PLL V21 C-0603 USB_PLLAVDD_1P2 DIO-TVS-BIPOLAR DIO-TVS-BIPOLAR RES RES_1 C225 C226 A 1% CAP_4 A 6.3V CAP_4 NOTE: If the USB port is not used in a design, then make the following changes to the schematic: TENDA Title W1800R & W80E Size Document Number Rev A2 Flash, USB 0.1 Date: Tuesday, February 19, 2013 Sheet 7 of 24 5 4 3 2 1

5 4 3 2 1 U9B BCM4706KPBG_0 Customer designs should use this circuit to save cost. BGA484P06-10 Change the parts to "loaded". TP1 4706_TRST_L A4 G22 TP2 4706_TDI E5 JTRST GPIO0/SPI_SCLK G21 VDD3_3 JTDI GPIO1/SPI_SS0 TP3 4706_TDO D5 F22 TP4 4706_TMS A5 JTDO GPIO2/SPI_MOSI G20 CAP_4 JTMS GPIO3/SPI_MISO TP5 4706_TCK C5 G19 JTCK GPIO4 RESET_53125 F19 GPIO5 GPIO5 E22 D C228 GPIO6/UART_RX2 D F21 UART_RX A19 GPIO7/UART_TX2 F20 UART_TX B19 UART_RX GPIO8/SPI_SS1 D21 UART_TX GPIO9/SPI_SS2 C22 J4 GPIO10/FLASH_CS2_L C21 1 GPIO11/FLASH_CS3_L B22 USB_LED UART_TX 2 GPIO12 USB_LED J21 B21 SYS_LED UART_RX 3 TDM0_SDIO GPIO13 SYS_LED H22 A22 WPS_PB 4 TDM0_WS GPIO14 J22 A21 WPS_LED TDM0_BITCLK GPIO15 WPS_LED HDR1X4-J J20 H21 TDM1_SDIO K22 TDM1_WS TDM1_BITCLK Optional WPS functionality. Remove along /RESET_L D19 RESET_L with the WPS LED, if not required. XTAL_IN AB12 E20 VDD3_3 XTAL_OUT AA12 XTALI OSC_XTAL_SEL XTALO C WPS Button Reset/WPS C 1 R78 RES_1 SW1 4 2 2 3 1 WPS_PB R79 SW TACT-SPST-RA C229 RES XTAL-1G3G CAP_4 Y2 1 3 4706_XOUT C230 C231 2 4 CAP CAP VDD3_3 B B R80 CAP U19 3 RES VCC C232 2 /RESET_L /RESET_L RESET GND C233 1 reset-809 CAP GND A A TENDA Title W1800R & W80E Size Document Number Rev B UART, GPIOs, RESET 0.1 Date: Tuesday, February 19, 2013 Sheet 8 of 24 5 4 3 2 1

5 4 3 2 1 R81 VDD3_3 1 2 EN_EEE R82 LED 1 2 GMII_LED_SEL Strap Function Setting Default RES_1 Polarity RES_1 Pin IMP_VOL_SEL Voltage used when IMP port is in RGMII mode: 0* 0 0=2.5V 1=1.5V - EN_EEE Strapping option: GMII_LED_SEL Strapping option: Enabled. Install R50 to disable. Set port 5 pins as LED signals. RGMII_VOL_SEL Voltage used when Port 5 is in RGMII mode: 0* 0 0=2.5V 1=1.5V - 1.2V R83 GMII_LED_SEL Port 5 signal select: 1 0 - 0=Port 5 signals 1=LED outputs @ 1A 2 1 EN_8051 EN_8051 Enable the embedded 8051 microcontroller: 0 1 For RES_1 0=Disable, 1=Enable - VDD3_3 NOTE: 53125 has an absolute 53125 MII_DUMB_FWDG_EN IMP port configuration: 1* 1 LED0: low EN_8051 Strapping option: 0=Require special header for all traffic CAP_4 CAP_4 maximum limit of 1.26V on FB D it's 1.2V pins. Only. FB5 Disable internal 8051. 1=Forward all traffic D CAP_4 VDD3_3 C235 C236 C237 LEDMODE[1:0] LED Mode (see datasheet for settings) 10 10 LED2: low LEDMODE[1:0] Strapping option: C234 Set LEDMODE = 10b SYS_FREQ[1:0] System clock: 00: 83MHz 01: 91MHz 10* 10 LED3: low U20C LEDMODE[1] has internal pullup. 10: 100MHz 11: 111MHz CAP_4 BCM53125SKMMLG-W1000-17822_8 AQFN186_0.4mm+6EP GMII_MODE[1:0] Interface Mode for WAN/port 5: 11* 11 LED4: low LED Functions 00: RGMII, 01: MII, 10: RvMII, 11: GMII LED5: low F21 C23 P_DRV Q1 SWREG_VDD PDRIVE 1 6 1G Speed (not used) IMP_MODE[1:0] IMP Port Mode: 00: RGMII 01:MII 00 11 LED6: high G1 D1 VDD1_2_E 100M Speed (not used) 10: RvMII 11:GMII LED7: high 2 5 IND L3 S2 S1 L16 CPU_EEPROM_SEL 0: Enable EEPROM Interface 1* 1 LED8: low K5 FSO 3 4 Link/Activity 1: Enable SPI & MDC/MDIO Interface K2 FSI G2 D2 FCS Duplex (not used) HW_FWDG_EN Fordwarding enabled at reset: 1* 1 LED9: low 2 J1 BF_1 R84 C238 C239 C240 FCLK 0=Disabled (needs S/W enable) RES_1 CAP_4 CAP_4 CAP_4 C25 N_DRV 1=Enabled (no S/W config needed) W1 NDRIVE EN_EEE Energy Efficient Ethernet: 1 1 - 1 EN_EEE U3 MOSI/DI MISO/DO/EN_EEE U1 SS/CS C241 0=Disabled 1=Enabled V2 SCK/SK CAP_4 * = Strapping option set at default with no option to change. 53125_XTAL_IN T2 F23 R3 XTAL_I VFB XTAL_O RES_1 XTAL-1G3G N1 53125_TRST 1 2 Y3 C17 TRST P5 F2 NC_1 TDI P2 EN_8051 R85 NC_2 TDO/EN_8051 1 3 53125_XOUT 1 R86 253125_XTAL_OUT M2 NC_3 TMS N3 NOTE: Route this connection with a A3 R1 RES_1 A25 NC_4 TCK separate trace from the output C242 C243 A27 NC_5 capacitors to the VFB pin. Do NOT 2 4 AD5 NC_6 connect the VFB pin directly to the CAP_4 NC_7 CAP_4 CAP_4 AE6 NC_8 NC_20 D2 VDD1_2_E plane! AG1 D28 AG5 NC_9 NC_21 F5 AG17 NC_10 NC_22 F25 AG29 NC_11 NC_23 G6 NC_12 NC_24 VDD3_3 AH26 H25 AJ3 NC_13 NC_25 T25 AJ27 NC_14 NC_26 Y25 1 CAP_4 CAP_4 B26 NC_15 NC_27 E22 C NC_16 NC_28 U9C C C1 AJ19 NC_17 NC_29 BCM4706KPBG_0 R88 RES_1 C21 E12 NC_18 NC_30 VDD2_5 BGA484P06-10 C29 AG9 NC_19 NC_31 J3 2 NC_32 U17 A20 G_MDC V17 GMAC_OVDD_25_33_1 MDC U20B C244 C245 C246 GMAC_OVDD_25_33_2 B20 G_MDIO BCM53125SKMMLG-W1000-17822_8 AF2 MDIO RESET_53125 RESET AQFN186_0.4mm+6EP L1 INT 1 G3 VSS AE1 R87 MDC AE3 MDIO J29 RES_1 IMP_GTXCLK W17 G_TXC P25 L29 G_RXC AB20 GMAC_TXCLK IMP_RXCLK IMP_TXCLK 2 GMAC_RXCLK Y17 G_TXCTRL N29 K28 G_RXCTRL W19 GMAC_TXEN AA18 N27 IMP_RXDV IMP_TXEN L27 GMAC_RXDV GMAC_TXER IMP_RXER IMP_TXER Y19 AB18 G_TXD0 R29 E29 V19 GMAC_RXER GMAC_TXD0 W16 G_TXD1 R27 IMP_RXD0 IMP_TXD0 G27 W18 GMAC_CRS GMAC_TXD1 AB19 G_TXD2 U27 IMP_RXD1 IMP_TXD1 H28 GMAC_COL GMAC_TXD2 Y18 G_TXD3 V28 IMP_RXD2 IMP_TXD2 K25 G_RXD0 AB22 GMAC_TXD3 P28 IMP_RXD3 IMP_TXD3 E27 G_RXD1 AB21 GMAC_RXD0 T28 IMP_RXD4 IMP_TXD4 F28 U20A GMAC_RXD1 IMP_RXD5 IMP_TXD5 G_RXD2 AA20 U29 G29 BCM53125SKMMLG-W1000-17822_8 GMAC_RXD2 IMP_RXD6 IMP_TXD6 CAP_4 CAP_4 CAP_4 G_RXD3 AA19 W29 J27 AQFN186_0.4mm+6EP GMAC_RXD3 IMP_RXD7 IMP_TXD7 AA16 AB14 P4_0P AH12 H5 SGMII_RXDP SGMII_TXDP TD0_P_4 LEDDATA/SYS_FREQ0 VDD1_2 AB16 AA14 P4_0N AJ13 G1 SGMII_RXDN SGMII_TXDN TD0_N_4 LEDCLK/LED_MODE0 E1 M25 P4_1P AH14 IMP_VOL_SEL IMP_VOL_REF TD1_P_4 U14 V14 P4_1N AG13 V5 SGMII_VDD_1P2_1 SGMII_VSS_1 TD1_N_4 LED_0/MII_DUMB_FWDG_EN W13 Y13 P4_2P AJ15 W3 SGMII_VDD_1P2_2 SGMII_VSS_2 TD2_P_4 LED_1 C247 C248 C249 W14 Y14 P4_2N AH16 Y2 P4_LNKACT SGMII_VDD_1P2_3 SGMII_VSS_3 TD2_N_4 LED_2/LED_MODE1 W15 Y15 P4_3P AH18 Y5 SGMII_VDD_1P2_4 SGMII_VSS_4 TD3_P_4 LED_3/SYS_FREQ1 AA13 Y16 P4_3N AJ17 SGMII_VDD_1P2_5 SGMII_VSS_5 TD3_N_4 AA15 AB13 AA3 SGMII_VDD_1P2_6 SGMII_VSS_6 LED_4/GMII_MODE0 AA17 AB15 P3_0P AH10 AB2 SGMII_VDD_1P2_7 SGMII_VSS_7 TD0_P_3 LED_5/GMII_MODE1 AB17 P3_0N AJ9 AC1 SGMII_VSS_8 P3_1P AJ7 TD0_N_3 LED_6/IMP_MODE0 AC3 P3_LNKACT Pins Pins Pins TD1_P_3 LED_7/IMP_MODE1 U13,U14 W12,W13, AA13, U13 Y12 P3_1N AH8 SGMII_PLLAVDD_1P2_1 SGMII_PLLAVSS_1 TD1_N_3 W12 AB11 P3_2P AG7 AB5 W14,W15 AA15, SGMII_PLLAVDD_1P2_2 SGMII_PLLAVSS_2 TD2_P_3 LED_8/CPU_EEPROM_SEL P3_2N AH6 AD2 AA17 1 1 P3_3P AH4 TD2_N_3 LED_9/HW_FWDG_EN R90 P3_3N AJ5 TD3_P_3 AJ23 TD3_N_3 GMII_RXD0/LED_10 P2_LNKACT RES_1 AH22 R89 P2_0P B8 GMII_RXD1/LED_11 AJ21 P2_0N A7 TD0_P_2 GMII_RXD2/LED_12 AH20 2 2 TD0_N_2 GMII_RXD3/LED_13 RES_1 P2_1P B6 AG23 P1_LNKACT P2_1N C7 TD1_P_2 GMII_RXD4/LED_14 AE20 P2_2P A5 TD1_N_2 GMII_RXD5/LED_15 AG21 P2_2N B4 TD2_P_2 GMII_RXD6/LED_16 AG19 B B P2_3P C3 TD2_N_2 GMII_RXD7/LED_17 TD3_P_2 P2_3N C5 TD3_N_2 GMII_RXDV/LED_18 AJ25 P0_LNKACT IMPMODE[1:0] Strapping option: AE22 P1_0P C11 GMII_RXER/LED_19 Set IMPMODE = 00b = RGMII P1_0N A11 TD0_P_1 AH24 P1_1P C13 TD0_N_1 GMII_RXCLK P1_1N B12 TD1_P_1 If the SGMII interface is used: Note: P1_2P A13 TD1_N_1 P1_2N B14 TD2_P_1 AC29 1) Add one or two more 0.1uF decoupling caps to the 1) Both the 53125 and the 4706 have built in series terminators for a 50ohm TD2_N_1 GMII_TXD0 P1_3P B16 TD3_P_1 GMII_TXD1 AB25 SGMII_VDD_1P2 pins. output impedance. All RGMII traces should have a 50-60ohm impedance. P1_3N A15 AE29 TD3_N_1 GMII_TXD2 AF28 2) Add the filter circuit for the SGMII_PLLAVDD_1P2 2) The TX traces, G_TXD[3:0] and G_TXCTRL, must be length matched to the G_TXC P0_0P B18 GMII_TXD3 AB28 pins as shown in the BCM94706nr reference design. trace length to within +/-100mils. Same for RX traces relative to G_RXC. P0_0N A19 TD0_P_0 GMII_TXD4 AC27 P0_1P B20 TD0_N_0 GMII_TXD5 AD28 P0_1N C19 TD1_P_0 GMII_TXD6 AE27 P0_2P A21 TD1_N_0 GMII_TXD7 P0_2N B22 TD2_P_0 Y28 P0_3P B24 TD2_N_0 GMII_TXEN AD25 P0_3N A23 TD3_P_0 GMII_TXER TD3_N_0 AA29 GMII_GTXCLK AA27 GMII_TXCLK GMII_LED_SEL H2 GMII_LED_SEL E3 AE24 RGMII_VOL_SEL GMII_VOL_REF R213 R313 R317 R321 R325 RES P4_0P 1 2 P4_TD0P RES RES RES RES P3_0N 1 2 P3_TD0N P2_0P 1 2 P2_TD0P P1_0N 1 2 P1_TD0N P0_0N 1 2 P0_TD0N L76 COM-MODE-CHOKE-14-23_16 L80 L84 L89 L93 COM-MODE-CHOKE-14-23_19 COM-MODE-CHOKE-14-23_16 COM-MODE-CHOKE-14-23_24 COM-MODE-CHOKE-14-23_26 P4_0N 4 3 P4_TD0N P3_0P 4 3 P3_TD0P P2_0N 4 3 P2_TD0N P1_0P 4 3 P1_TD0P P0_0P 4 3 P0_TD0P R306 R329 R336 R337 R341 RES RES RES RES RES R307 R314 R318 R322 R326 RES RES RES RES P4_1N 1 2 P4_TD1N P3_1P 1 2 P3_TD1P P2_1N 1 2 P2_TD1N P1_1P 1 2 P1_TD1P RES P0_1P 1 2 P0_TD1P L77 L81 L85 L88 COM-MODE-CHOKE-14-23_17 COM-MODE-CHOKE-14-23_16 COM-MODE-CHOKE-14-23_22 COM-MODE-CHOKE-14-23_16 L92 COM-MODE-CHOKE-14-23_16 A P4_1P 4 3 P4_TD1P P3_1N 4 3 P3_TD1N P2_1P 4 3 P2_TD1P P1_1N 4 3 P1_TD1N A P0_1N 4 3 P0_TD1N R310 R330 R335 R338 R342 RES RES RES RES RES R308 R315 R319 R323 R327 RES RES RES RES RES P4_2P 1 2 P4_TD2P P3_2N 1 2 P3_TD2N P2_2P 1 2 P2_TD2P P1_2N 1 2 P1_TD2N P0_2N 1 2 P0_TD2N L78 L82 L86 L91 L95 COM-MODE-CHOKE-14-23_16 COM-MODE-CHOKE-14-23_20 COM-MODE-CHOKE-14-23_16 COM-MODE-CHOKE-14-23_23 COM-MODE-CHOKE-14-23_25 P4_2N 4 3 P4_TD2N P3_2P 4 3 P3_TD2P P2_2N 4 3 P2_TD2N P1_2P 4 3 P1_TD2P P0_2P 4 3 P0_TD2P R311 R331 R334 R339 R343 RES RES RES RES RES R309 R316 R320 R324 R328 P4_3N RES 1 2 P4_TD3N P3_3P RES 1 2 P3_TD3P P2_3N RES 1 2 P2_TD3N P1_3P RES 1 2 P1_TD3P P0_3P RES 1 2 P0_TD3P TENDA Title L79 COM-MODE-CHOKE-14-23_18 L83 COM-MODE-CHOKE-14-23_16 L87 COM-MODE-CHOKE-14-23_21 L90 COM-MODE-CHOKE-14-23_16 L94 COM-MODE-CHOKE-14-23_16 W1800R & W80E P4_3P 4 3 P3_3N 4 3 P2_3P 4 3 P1_3N 4 3 P0_3N 4 3 P4_TD3P P3_TD3N P2_TD3P P1_TD3N P0_TD3N Size Document Number Rev R312 R332 R333 R340 R344 Custom GigE Switch 0.1 RES RES RES RES RES Date: Tuesday, February 19, 2013 Sheet 9 of 24 5 4 3 2 1

5 4 3 2 1 U20D BCM53125SKMMLG-W1000-17822_8 VDD1_2_E AQFN186_0.4mm+6EP DVDD decoupling VDD1_2_E PR0 M5 PR1 AVDDL_1 DVDD_1 AA1 PR2 AVDDL_1 DVDD_2 AE18 C250 C251 C252 C253 C254 C255 C256 C257 C258 AVDDL_1 DVDD_3 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 PR3 AG25 AVDDL_1 DVDD_4 FB_0 D PR4 V25 D PR5 AVDDL_1 DVDD_5 M28 AVDDL_1 DVDD_6 E20 DVDD_7 VDD3_3 VDD2_5 Pin E20 Pin AG25 Pin V25 Pin AA1 Pin AE18 Pin M28 Pin M5 Pin E20 FB6 PR16 PHY_BVDD PR17 AVDDL_2 PR6 PR18 AVDDL_2 OVDD PR7 C259 C260 C261 C262 C263 PR19 AVDDL_2 OVDD PR8 AVDDL_2 OVDD CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 300mA VDD3_3 PR9 OVDD VDD3_3 AE8 AVDDH_1 FB_0 AE10 PR20 AVDDH_2 OVDD2 Pin AJ11 Pin C9 Pin C15 AE14 AVDDH_3 OVDD2 PR21 AG15 PR22 VDD1_2_E E18 AVDDH_4 OVDD2 PR23 FB7 E14 AVDDH_5 OVDD2 PR24 AVDDH_6 OVDD2 CAP_4 CAP_4 CAP_4 FB_0 EGPHY_PLLVDD E10 PR25 AVDDH_7 OVDD2 E8 AVDDH_8 OVDD2 PR26 OVDD decoupling OVDD2 decoupling CAP_4 CAP_4 CAP_4 C264 C265 C266 300mA CAP_4 VDD3_3 VDD2_5 VDD3_3 C15 PR10 FB8 C9 EGPHY_BVDD OVDD3 PR11 XTALAVDD QGPHY1_BVDD OVDD3 FB_0 AJ11 PR12 QGPHY2_BVDD OVDD3 PR13 C267 C268 C269 C270 C271 C272 C273 OVDD3 CAP_4 CAP_4 CAP_4 PR14 300mA C A17 OVDD3 PR15 C VDD1_2_E A9 EGPHY_PLLVDD OVDD3 FB9 AG11 QGPHY1_PLLVDD W27 QGPHY2_PLLVDD OTP_VDD QGPHY1_PLLVDD Pin PR1 Pin PR5 T5 C274 C275 C276 AD17 XTAL_AVDD PLL_AVDD CAP_4 CAP_4 300mA E16 RDAC_0 EGPHY_RDAC CAP_4 B10 RDAC_1 QGPHY1_RDAC H EPAD QGPHY2_RDAC AE12 RDAC_2 OTP_VDD decoupling OVDD3 decoupling FB_0 1 1 1 VDD3_3 VDD3_3 R91 R92 R93 VDD1_2_E CAP_4 CAP_4 FB10 1% 1% 1% C280 C281 RES_1 RES_1 RES_1 QGPHY2_PLLVDD 2 2 2 CAP_4 CAP_4 C277 C279 CAP_4 CAP_4 300mA C278 Pin W27 Pin PR2 AVDDL decoupling FB_0 VDD1_2_E CAP_4 CAP_4 VDD1_2_E B FB11 B PLL_AVDD C285 C286 C287 C282 C283 C284 CAP_4 CAP_4 CAP_4 300mA Pin PR0 Pin PR4 VDD3_3 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 AVDDH decoupling C288 C289 C290 C291 C292 C293 Pins Pin E18 Pins Pin E14 Pins E8, AE8, AE14, E10 A AE10 AG15 A TENDA Title W1800R & W80E Size Document Number Rev Custom 53125 Power 0.1 Date: Tuesday, February 19, 2013 Sheet 10 of 24 5 4 3 2 1

5 4 3 2 1 CAP_1 T2 CAP_1 T2 2 C294 1 2 C295 1 VDD3_3 T1A T1B 1CT:1CT 1CT:1CT R94 CAP_1 1 36 PX2_7 CAP_1 10 27 PX1_1 1 2 D7 WAN P2_TD3P P1_TD0P P0_LNKACT 2 C296 1 2 C299 1 RES_1 DIO-LED_2 C300 CAP_1 CAP_1 P2_TD3N P1_TD0N 2 C297 1 2 35 PX2_8 2 C301 1 11 26 PX1_2 CAP_4 CAP_1 3 1CT:1CT 34 PX2_5 CAP_1 12 1CT:1CT 25 PX1_6 P2_TD2N P1_TD1N 2 C298 1 2 C302 1 CAP_1 CAP_1 P2_TD2P P1_TD1P R95 2 C303 1 4 33 PX2_4 2 C304 1 13 24 PX1_3 1 2 D8 LAN 1 P1_LNKACT CAP_1 5 1CT:1CT 32 PX2_3 CAP_1 14 1CT:1CT 23 PX1_4 RES_1 DIO-LED_2 C307 P2_TD1P P1_TD2P 2 C305 1 2 C306 1 D CAP_4 D CAP_1 CAP_1 P2_TD1N P1_TD2N 2 C308 1 6 31 PX2_6 2 C309 1 15 22 PX1_5 CAP_1 7 1CT:1CT 30 PX2_2 CAP_1 16 1CT:1CT 21 PX1_8 P2_TD0N P1_TD3N 2 C310 1 2 C311 1 R96 1 2 D9 LAN 2 P2_LNKACT P2_TD0P P1_TD3P 8 29 PX2_1 17 20 PX1_7 RES_1 DIO-LED_2 C312 2 C313 1 9 28 2 C314 1 18 19 CAP_4 R97 CAP_1 R98 CAP_1 RES_0 RES_0 R99 1 2 D10 IPTV P4_LNKACT 2 C316 J5 2 C315 PX4_1 25 RES_1 DIO-LED_2 C317 CAP_1 PX4_2 26 1 CAP_1 PX4_3 27 CAP_4 1 PX4_4 28 PX4_5 29 PX4_6 30 PX4_7 31 PX4_8 32 R100 PX3_1 17 1 2 D11 LAN 3 P3_LNKACT PX3_2 18 PX3_3 19 RES_1 DIO-LED_2 PX3_4 20 C318 PX3_5 21 PX3_6 22 CAP_4 PX3_7 23 PX3_8 24 PX2_1 9 LAN 3 LED is active high due to the IMP_MODE0 strapping option on page 5. PX2_2 10 CAP_1 CAP_1 PX2_3 11 2 C319 1 T2A 2 C320 1 T2B PX2_4 12 T2 T2 PX2_5 13 CAP_1 1 1CT:1CT 36 PX4_7 CAP_1 10 1CT:1CT 27 PX3_1 PX2_6 14 P4_TD3P P3_TD0P 2 C321 1 2 C322 1 PX2_7 15 PX2_8 16 NOTE: 100pF caps on LED signals are optional bypass caps to supress EMI CAP_1 CAP_1 P4_TD3N P3_TD0N radiation from long LED traces. Place caps near LEDs. 2 C324 1 2 35 PX4_8 2 C323 1 11 26 PX3_2 PX1_1 1 PX1_2 2 C CAP_1 3 1CT:1CT 34 PX4_5 CAP_1 12 1CT:1CT 25 PX3_6 PX1_3 3 C P4_TD2N P3_TD1N 2 C325 1 2 C326 1 PX1_4 4 R101 WLAN_2G_ACT WLAN_2G_ACT 1 2 D12 PX1_5 5 C328 CAP_1 CAP_1 PX1_6 6 RES_1 WLAN 2.4GHz Activity P4_TD2P P3_TD1P DIO-LED_2 2 C327 1 4 33 PX4_4 2 C329 1 13 24 PX3_3 PX1_7 7 CAP_4 PX1_8 8 CAP_1 5 1CT:1CT 32 PX4_3 CAP_1 14 1CT:1CT 23 PX3_4 P4_TD1P P3_TD2P 2 C330 1 2 C331 1 R113 GPIO5 1 2 RJ45x4_1 CAP_1 CAP_1 RES_1 P4_TD1N P3_TD2N 2 C332 1 6 31 PX4_6 2 C333 1 15 22 PX3_5 R102 WLAN_CARD_ACT 1 2 D13 WLAN 5GHz Activity CAP_1 7 1CT:1CT 30 PX4_2 CAP_1 16 1CT:1CT 21 PX3_8 P4_TD0N P3_TD3N RES_1 C336 2 C334 1 2 C335 1 DIO-LED_2 CAP_4 P4_TD0P P3_TD3P 8 29 PX4_1 17 20 PX3_7 2 1 9 28 2 1 18 19 WPS LED C337 R104 C338 R105 R103 WPS_LED WPS_LED 1 2 D14 C339 CAP_1 RES_0 CAP_1 RES_0 RES_1 DIO-LED_2 CAP_4 USB LED R106 USB_LED 1 2 D15 2 C342 USB_LED C340 2 C341 RES_1 DIO-LED_2 CAP_1 CAP_4 1 CAP_1 1 SYS_LED R107 SYS_LED 1 2 T3 CAP_1 RES_1 C346 D16 2 C343 1 T_1 1 1CT:1CT 18 PX0_1 System LED P0_TD0P CAP_4 DIO-LED_2 CAP_1 J6 2 C344 1 PX0_1 1 P0_TD0N CAP_1 2 17 PX0_2 PX0_2 2 PIN1 2 C345 1 PX0_3 3 PIN2 B PIN3 B 3 1CT:1CT 16 PX0_6 PX0_4 4 P0_TD1N CAP_1 PX0_5 5 PIN4 2 C347 1 PX0_6 6 PIN5 VDD3_3 PX0_7 7 PIN6 P0_TD1P PIN7 R108 CAP_1 4 15 PX0_3 PX0_8 8 PIN8 1 2 2 C348 1 5 1CT:1CT 14 PX0_4 R_1 D17 Power LED P0_TD2P CAP_1 2 C349 1 RJ45-10+2-J_2 DIO-LED_2 P0_TD2N CAP_1 6 13 PX0_5 2 C350 1 7 1CT:1CT 12 PX0_8 P0_TD3N CAP_1 2 C351 1 P0_TD3P 8 11 PX0_7 CAP_1 2 C352 1 9 10 R109 1 C353 2 CAP_1 RES_0 NOTE: 1、Place magnetic close to RJ45 . 2、The 75R resistors should be placed closed to the magnetic . The prupouse of the resistors is to suppress EMI radiation. Port State Function LAN/WAN LINK/ACT Ethernet Link/Activity WPS WPS Status WLAN 2.4GHz UP/ACT 2.4GHz Up/Activity WLAN 5GHz UP/ACT 5GHz Up/Activity A A TENDA Title W1800R & W80E Size Document Number Rev Custom Ethernet Ports and LEDs 0.1 Date: Tuesday, February 19, 2013 Sheet 11 of 24 5 4 3 2 1

5 4 3 2 1 For a full sized mini-Card, install J15 and no-load J14 For a half sized mini-Card, install J14 and (optionally) no-load J15 Place close to 24 REFCLK5GP 1 R111 2 RC5P REFCLK_P REFCLK_P D C358 D RES_1 CAP_4 1 REFCLK5GNR115 2 RC5N REFCLK_N REFCLK_N C362 RES_1 1 CAP_4 1 RES_1 RES_1 R114 R117 2 2 CAP_4 1 REFCLK2GPR121 2 C367 RES_1 C370 CAP_4 REFCLK2GN 1 R124 2 1 1 RES_1 RES_1 RES_1 R125 R126 2 2 U9A BCM4706KPBG_0 BGA484P06-10 M18 100M_PCIE_CLK0P N22 Place close to U9 L18 100M_PCIE_CLK0N PCIE_REFCLKP PCIE_REFCLKOUTP N21 PCIE_REFCLKN PCIE_REFCLKOUTN C C CAP_4 PCIE_0_TDP PCIE_0_TDP PCIE0_RDP PCIE0_RDP L19 N19 PCIE0_TDP C373 PCIE0_RDN L20 PCIE0_RDP PCIE0_TDP N20 PCIE0_TDN C374 PCIE0_RDN PCIE0_RDN PCIE0_TDN PCIE_0_TDN PCIE_0_TDN K21 PCIE0_RST_L PCIE0_RST_L PCIE0_RST_L CAP_4 PCIE1_RDP M21 PCIE1_RDN M22 PCIE1_RDP C378 C375 PCIE1_RDN P21 PCIE1_TDP CAP_4 CAP_4 PCIE1_TDP P22 PCIE1_TDN PCIE1_TDN L22 PCIE1_RST_L PCIE1_RST_L RES_1 K19 PCIE_SDVDD_1P2 L21 PCIE_SDVDD_1P2_1 M17 PCIE_SDVDD_1P2_2 K16 M19 PCIE_SDVDD_1P2_3 PCIE_SDVSS_1 K20 P19 PCIE_SDVDD_1P2_4 PCIE_SDVSS_2 M20 R21 PCIE_SDVDD_1P2_5 PCIE_SDVSS_3 N17 2.4GHz PCIE_SDVDD_1P2_6 PCIE_SDVSS_4 N18 VDD3_3 PCIE_SDVSS_5 1 R22 R136 PCIE_SDVSS_6 REFCLK_2G_P 1 P20 PCIE_PLLVDD_1P2 K18 REFCLK_2G_N U25A PCIE_PLLVDD_1P2 PCIE_PLLVSS BCM4331KMLG-W1000-17503_2 2 88 70 R137 C381 89 REFCLKP SPROM_CS 73 RES_1 2 REFCLKN SPROM_CLK 74 CAP_4 PCIE_2G_TDP 86 SPROM_DIN 75 PCIE_2G_TDN 85 TDP0 SPROM_DOUT CAP_4 TDN0 PCIE_2G_RDN 91 C382 PCIE_2G_RDP 92 RDP0 RDN0 C385 C386 95 VDD1_2 CAP_4 CAP_4 77 PERST_L PCIE_CLKREQ_L FB13 Place close to U9 PCIE_PLLVDD_1P2 VDD3_3 78 PCI_PME_L CAP_4 CAP_4 CAP_4 B FB_0 C388 C389 CAP_4 79 B RF_DISABLE_L C387 2A Place close to U25 C390 PCIE_2G_RST_L C394 C395 C393 CAP_4 CAP_4 CAP_4 R138 1 2 VDD1_2 IND-SHIELDED-NO-DOT RES_1 L17 1 2 PCIE_SDVDD_1P2 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 C399 C400 C401 C402 C403 C404 C398 Pin K19 Pin L21 Pin P19 Pin R21 Pin M17 & M19 VDD3_3 BOX B U26 50 Ohm Place them close to ICS8557 trace 50 Ohm trace CAP NP_7 L_0 15 20 SRC_100M_PCIE_CLK0P 2 R139 1 R_4 C406 1 2 CAP NP_7 100M_PCIE_CLK0P L18 VDDODA CLK0P 1 2 CAP NP_7 1 19 SRC_100M_PCIE_CLK0N 2 R140 1 R_4 C409 1 2 CAP NP_7 100M_PCIE_CLK0N C405 VDDXD CLK0N A 1 2 5 18 REFCLK5GP A 1 1 1 C408 C410 C411 X1 CLK1P 1 1 C407 17 REFCLK5GN 100 Ohm differential pair 2 2 Y4 2 CLK1N CAP NP_7 CAP NP_7 CAP NP_7 R141 R142 14 REFCLK2GP 2 2 2 XTAL-1G3G_7 2 CLK2P R_4 R_4 4 13 REFCLK2GN CAP NP_7 CLK2N 1 C412 2 6 12 1 1 3 X2 CLK3P 11 R143 2 1 R_4 2 CLK3N R144 2 1 R_4 3 S0 8 R145 2 1 R_4 4 S1 OE 7 9 S2 PD 10 16 GNDXD IREF TENDA 1 GNDODA ICS8557 R146 R_4 Title W1800R & W80E Size Document Number Rev 2 A2 4706 and 4331 PCIe 0.1 Date: Tuesday, February 19, 2013 Sheet 12 of 24 5 4 3 2 1

5 4 3 2 1 CAP_4 CAP_4 U9G U9H U9F BCM4706KPBG_0 BCM4706KPBG_0 BCM4706KPBG_0 BGA484P06-10 BGA484P06-10 VDD1_2 BGA484P06-10 VDD1_2 FB14 B2 H16 M16 T2 G9 AA21 CORE_PLLAVDD_1P2 B3 DVSS_1 DVSS_51 H17 N3 DVSS_101 DVSS_141 T3 G11 CORE_DVDD_1P2_1 CORE_PLLAVDD_1P2 B4 DVSS_2 DVSS_52 J4 N5 DVSS_102 DVSS_142 T4 G13 CORE_DVDD_1P2_2 C413 C414 FB_0 B5 DVSS_3 DVSS_53 J5 N6 DVSS_103 DVSS_143 T5 H10 CORE_DVDD_1P2_3 300mA CAP_4 B7 DVSS_4 DVSS_54 J6 N7 DVSS_104 DVSS_144 T6 H12 CORE_DVDD_1P2_4 6.3V C415 B9 DVSS_5 DVSS_55 J8 N9 DVSS_105 DVSS_145 T7 H14 CORE_DVDD_1P2_5 DVSS_6 DVSS_56 DVSS_106 DVSS_146 CORE_DVDD_1P2_6 CAP_4 B11 J9 N10 T8 J7 Y20 DVSS_7 DVSS_57 DVSS_107 DVSS_147 CORE_DVDD_1P2_7 CORE_PLL_AVSS CAP_4 B13 J10 N11 T10 K14 D B15 DVSS_8 DVSS_58 J11 N12 DVSS_108 DVSS_148 T11 L7 CORE_DVDD_1P2_8 VDD1_2 D B17 DVSS_9 DVSS_59 J12 N13 DVSS_109 DVSS_149 T12 L9 CORE_DVDD_1P2_9 FB15 C4 DVSS_10 DVSS_60 J13 N14 DVSS_110 DVSS_150 T13 M14 CORE_DVDD_1P2_10 Y21 MISC1_PLLAVDD_1P2 C6 DVSS_11 DVSS_61 J14 N15 DVSS_111 DVSS_151 T15 N8 CORE_DVDD_1P2_11 MISC1_PLLAVDD_1P2 C8 DVSS_12 DVSS_62 J15 N16 DVSS_112 DVSS_152 T16 P14 CORE_DVDD_1P2_12 C416 C417 FB_0 C10 DVSS_13 DVSS_63 J16 P5 DVSS_113 DVSS_153 T17 R8 CORE_DVDD_1P2_13 300mA CAP_4 C12 DVSS_14 DVSS_64 J17 P6 DVSS_114 DVSS_154 T18 R11 CORE_DVDD_1P2_14 6.3V C418 C14 DVSS_15 DVSS_65 J18 P7 DVSS_115 DVSS_155 U3 T9 CORE_DVDD_1P2_15 DVSS_16 DVSS_66 DVSS_116 DVSS_156 CORE_DVDD_1P2_16 CAP_4 CAP_4 C16 K3 P8 U4 T14 W20 C20 DVSS_17 DVSS_67 K5 P9 DVSS_117 DVSS_157 U5 CORE_DVDD_1P2_17 MISC1_PLLAVSS D2 DVSS_18 DVSS_68 K6 P10 DVSS_118 DVSS_158 U6 VDD3_3 VDD1_2 D4 DVSS_19 DVSS_69 K7 P11 DVSS_119 DVSS_159 U7 FB16 E18 DVSS_20 DVSS_70 K8 P12 DVSS_120 DVSS_160 U8 C19 W21 MISC2_PLLAVDD_1P2 E21 DVSS_21 DVSS_71 K9 P13 DVSS_121 DVSS_161 U9 D18 INT_OVDD_33_1 MISC2_PLLAVDD_1P2 F4 DVSS_22 DVSS_72 K10 P15 DVSS_122 DVSS_162 U10 D22 INT_OVDD_33_2 C419 C420 FB_0 F6 DVSS_23 DVSS_73 K11 P16 DVSS_123 DVSS_163 U11 E19 INT_OVDD_33_3 300mA CAP_4 F8 DVSS_24 DVSS_74 K12 P17 DVSS_124 DVSS_164 U12 F5 INT_OVDD_33_4 6.3V C421 F10 DVSS_25 DVSS_75 K13 P18 DVSS_125 DVSS_165 U15 F7 INT_OVDD_33_5 F12 DVSS_26 DVSS_76 K15 R3 DVSS_126 DVSS_166 U16 F9 INT_OVDD_33_6 V20 F14 DVSS_27 DVSS_77 K17 R5 DVSS_127 DVSS_167 U18 F11 INT_OVDD_33_7 MISC2_PLLAVSS F16 DVSS_28 DVSS_78 L3 R6 DVSS_128 DVSS_168 V2 F13 INT_OVDD_33_8 VDD3_3 F18 DVSS_29 DVSS_79 L5 R7 DVSS_129 DVSS_169 V3 F15 INT_OVDD_33_9 FB17 G2 DVSS_30 DVSS_80 L6 R9 DVSS_130 DVSS_170 V7 F17 INT_OVDD_33_10 AA11 XTAL_PLLAVDD_3P3 G4 DVSS_31 DVSS_81 L8 R12 DVSS_131 DVSS_171 V8 G18 INT_OVDD_33_11 XTAL_PLLAVDD_3P3 DVSS_32 DVSS_82 DVSS_132 DVSS_172 INT_OVDD_33_12 CAP_4 CAP_4 G5 L10 R13 V9 C422 C423 FB_0 G6 DVSS_33 DVSS_83 L11 R14 DVSS_133 DVSS_173 V12 300mA CAP_4 G7 DVSS_34 DVSS_84 L12 R15 DVSS_134 DVSS_174 V15 10V C424 G8 DVSS_35 DVSS_85 L13 R16 DVSS_135 DVSS_175 V16 D17 U21 G10 DVSS_36 DVSS_86 L14 R17 DVSS_136 DVSS_176 V18 E4 NC_D17 NC_U21 V11 G12 DVSS_37 DVSS_87 L15 R18 DVSS_137 DVSS_177 W4 H18 NC_E4 NC_V11 V13 G14 DVSS_38 DVSS_88 L16 R19 DVSS_138 DVSS_178 Y5 H19 NC_H18 NC_V13 W22 G15 DVSS_39 DVSS_89 L17 T1 DVSS_139 DVSS_179 AA6 H20 NC_H19 NC_W22 Y11 G16 DVSS_40 DVSS_90 M4 DVSS_140 DVSS_180 AA8 J19 NC_H20 NC_Y11 Y22 G17 DVSS_41 DVSS_91 M5 DVSS_181 T20 NC_J19 NC_Y22 AA22 H3 DVSS_42 DVSS_92 M6 NC_T20 NC_AA22 H5 DVSS_43 DVSS_93 M7 H6 DVSS_44 DVSS_94 M9 H7 DVSS_45 DVSS_95 M10 H9 DVSS_46 DVSS_96 M11 C H11 DVSS_47 DVSS_97 M12 C DVSS_48 DVSS_98 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 H13 M13 DVSS_49 DVSS_99 H15 DVSS_50 DVSS_100 M15 CORE_DVDD_1P2 Decoupling CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 VDD1_2 C425 C426 C427 C428 C429 C430 C431 C432 C433 C434 C435 C436 C437 C438 C439 C440 C441 C442 Pin G9 Pin G11 Pin G13 Pin H10 Pin H12 Pin H14 Pin J7 Pin K14 Pin L7 Pin L9 Pin M14 Pin N8 Pin P14 Pin R8 Pin R11 Pin T9 Pin T14 CAP_4 INT_OVDD_33 Decoupling CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 VDD3_3 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 C443 C444 C445 C446 C447 C448 C449 C450 C451 C452 C453 C454 C455 Pin C19 Pin D18 Pin D22 Pin E19 Pin F5 Pin F7 Pin F9 Pin F11 Pin F13 Pin F15 Pin F17 Pin G18 B B A A TENDA Title W1800R & W80E Size Document Number Rev C 4706 Voltages, Grounds 0.1 Date: Tuesday, February 19, 2013 Sheet 13 of 24 5 4 3 2 1

5 4 3 2 1 VDD1_2_RF_2.4G Pin 17 Pins 63 & 67 Pin 71 Pin 81 Pin 100 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 C457 C458 C459 C460 C461 C462 C463 C464 C465 VDD3_3 C456 CAP CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 C466 C467 C468 C469 C470 C471 C472 C473 C474 C475 C476 C477 U25C CAP_4 BCM4331KMLG-W1000-17503_2 17 VDD_17 VDDIO_1 1 Pin 16 Pin 68 Pin 76 Pin 80 Pin 94 63 VDD_63 VDDIO_16 16 Pin 1 67 68 VDD1_2_RF_2.4G 71 VDD_67 VDDIO_68 76 81 VDD_71 VDDIO_76 80 VDD_81 VDDIO_80 CAP_4 CAP_4 100 94 VDD3_3 VDD3_3 VDD_100 OTP_VDD/VDDIO Pins 84 & 87 Pin 87 Pin 90 Pin 93 CAP_4 D D 84 9 CAP_4 1 R147 2 C478 C479 C480 C481 C482 C483 C484 C485 87 VDD/TVDD VDD3P3_LDO 90 TVDD/PVDD 48 PA_2G_CORE0_3P3_2G C486 C487 C489 C490 C491 RES_1 PVDD/RVDD PA_2G_CORE0_VDD3P3 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 VDD1_2A_2G 93 40 PA_2G_CORE1_3P3_2G RVDD/VDD PA_2G_CORE1_VDD3P3 32 PA_2G_CORE2_3P3_2G 21 PA_2G_CORE2_VDD3P3 C488 GPIO_VDD1P2 42 PA_5G_CORE0_3P3_2G CORE0_VDD1P2_2G 46 PA_5G_CORE0_VDD3P3 34 PA_5G_CORE1_3P3_2G CORE0_VDD1P2 PA_5G_CORE1_VDD3P3 CAP_4 CORE1_VDD1P2_2G 38 26 PA_5G_CORE1_3P3_2G CORE2_VDD1P2_2G 30 CORE1_VDD1P2 PA_5G_CORE2_VDD3P3 CORE2_VDD1P2 51 VREG3P3_4331_2G VDD3_3 TX_CORE0_VDD1P2_2G 44 VREG3P3_VDD3P3 TX_CORE1_VDD1P2_2G 36 TX_5G2G_CORE0_VDD1P2 60 RFLDO_3P3_IN_2G 1 R148 2 TX_CORE2_VDD1P2_2G 28 TX_5G2G_CORE1_VDD1P2 I_VDD_RFLDO 59 TX_5G2G_CORE2_VDD1P2 O_VDD1P3_RF 61 RFLDO_VREF_2G 4331_RF_LDO_2G C492 RES_1 LOGEN_VDD1P2_2G 52 O_VREF_LDO C494 SYNTH_VCO_1P2_2G 53 LOGEN_VDD1P2 22 RCALRES_2G C493 CAP_4 SYNTH_VCO_VDD1P2 RCAL_EXT_RES CAP_4 SYNTH_1P2_2G 54 SYNTH_VDD1P2 1 CAP_4 VDDPLL_1P2_2G 62 101 R149 VDDPLL GND_SLUG VDD3_3 RES_1 2 VDD1_2_RF_2.4G VDD1_2A_2G 1 R150 2 RES_1 C495 C496 C497 C498 C140 C125 C354 CAP CAP CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 6.3V VDD1_2A_2G 1 R151 2 CORE0_VDD1P2_2G VDD3_3 C RES_1 C499 C500 RES_1 C CAP_4 CAP_4 1 R152 2 1 R153 2 PA_2G_CORE0_3P3_2G RES_1 C501 C502 C503 CAP_4 CAP_4 CAP_4 VDD1_2A_2G 1 R154 2 CORE1_VDD1P2_2G RES_1 C504 C505 PA_5G_CORE0_3P3_2G CAP_4 CAP_4 4331_RF_LDO_2G CAP_4 CAP_4 C506 VDD3_3 CAP_4 1 R155 2 LOGEN_VDD1P2_2G RES_1 C507 C508 C509 VDD1_2A_2G CAP_4 VDD3_3 RES_1 C177 C126 C355 1 R156 2 CORE2_VDD1P2_2G CAP CAP CAP_4 1 R157 2 1 R158 2 PA_2G_CORE1_3P3_2G RES_1 C510 C511 CAP_4 CAP_4 RES_1 C514 C512 C513 4331_RF_LDO_2G CAP_4 CAP_4 CAP_4 CAP_4 CAP_4 1 R159 2 SYNTH_VCO_1P2_2G RES_1 C515 C516 C517 CAP_4 PA_5G_CORE1_3P3_2G C518 CAP_4 B B CAP_4 CAP_4 4331_RF_LDO_2G VDD1_2A_2G 1 R160 2 SYNTH_1P2_2G 1 R161 2 TX_CORE0_VDD1P2_2G RES_1 C519 C522 C523 RES_1 RES_1 C520 C521 CAP_4 CAP_4 1 R162 2 PA_2G_CORE2_3P3_2G CAP_4 C524 C525 CAP_4 CAP_4 CAP_4 CAP_4 4331_RF_LDO_2G VDD1_2A_2G 1 R163 2 VDDPLL_1P2_2G 1 R164 2 TX_CORE1_VDD1P2_2G RES_1 C526 C527 C528 PA_5G_CORE1_3P3_2G RES_1 C530 C531 CAP_4 CAP_4 C529 CAP_4 CAP_4 VDD1_2A_2G 1 R165 2 TX_CORE2_VDD1P2_2G RES_1 C532 C533 CAP_4 CAP_4 A A TENDA Title W1800R & W80E Size Document Number Rev C 2.4GHz 4331 Power & Ground 0.1 Date: Tuesday, February 19, 2013 Sheet 14 of 24 5 4 3 2 1

5 4 3 2 1 U25B BCM4331KMLG-W1000-17503_2 D 47 14 D RXG_0 RF_2G_ANTENNA_CORE0 MIMOPHY_CORE0_ANT0_RX C0A0RX_2G 39 5 RXG_1 RF_2G_ANTENNA_CORE1 MIMOPHY_CORE0_ANT0_TX C0A0TX_2G 31 18 RXG_2 RF_2G_ANTENNA_CORE2 MIMOPHY_CORE1_ANT0_RX C1A0RX_2G 45 15 RF_5G_ANTENNA_CORE0 MIMOPHY_CORE1_ANT0_TX C1A0TX_2G 37 20 RF_5G_ANTENNA_CORE1 MIMOPHY_CORE2_ANT0_RX C2A0RX_2G 29 19 RF_5G_ANTENNA_CORE2 MIMOPHY_CORE2_ANT0_TX C2A0TX_2G 49 25 TXG_0 PA_2G_CORE0 TSSI0 TSSI_2G_0 41 24 TXG_1 PA_2G_CORE1 TSSI1 TSSI_2G_1 33 23 TXG_2 PA_2G_CORE2 TSSI2 TSSI_2G_2 43 35 PA_5G_CORE0 13 PAVREF_PAR_2G 27 PA_5G_CORE1 VDD2P5_PAR 12 PA_5G_CORE2 VDD2P5_PAR_A PA_2G_VREF_0 11 TP6 4331_2G_TRST_L 65 VDD2P5_PAR_B 10 C534 GPIO_0/TRST_L VDD2P5_PAR_C PA_2G_VREF_1 99 8 VDD3_3 GPIO_3/TDI VDD2P5_PAR_D CAP_4 TP8 4331_2G_TDO 66 7 GPIO_2/TDO VDD2P5_PAR_E PA_2G_VREF_2 96 6 VDD3_3 TP10 4331_2G_TCK 69 GPIO_4/TMS/EXT_BT_SHD0 VDD2P5_PAR_F R166 GPIO_1/TCK 2 1 POR_L_2G 97 50 98 GPIO_5/POR_L/BT_SHD1 NC RES_1 LNA_2G_PU_0 82 GPIO_6/EXT_LNA_0_G LNA_2G_PU_1 GPIO_7/EXT_LNA_1_G 2 R167 83 LNA_2G_PU_2 2 GPIO_8/EXT_LNA_2_G GPIO_9/EXT_LNA_0_A RES_1 3 C 4 GPIO_10/EXT_LNA_1_A C 72 GPIO_11/EXT_LNA_2_A 1 WLAN_2G_ACT GPIO_12 JTAG_SEL_2G 64 JTAG_SEL 2 R168 4331_2G_XIN 56 4331_2G_XOUT 55 XTAL_IN XTAL_OUT RES_1 58 57 XTAL_BUF_OUT O_XTAL_VDD2P5 X2P5_2G XTAL-1G3G 1 Y5 RES_1 1 3 4331_XOUT_2G 1 R169 2 C535 C536 C537 2 4 VDD3_3 CAP_4 CAP_4 CAP_4 R170 R171 1 2 C0A0TX_2G 1 2 C1A0TX_2G RES_1 RES_1 B MIMOPHY_CORE0_ANT0_TX Strapping Option: MIMOPHY_CORE1_ANT0_TX Strapping Option: B Do not use OTP for configuration. Set SROM present so NVRAM can configure 4331. 4331 Function Setting Default Strapping Pull Option Pin MIMOPHY_CORE0_ANT0_TX 0 = Do not use OTP for configuration (setting) 0 PU 1 = Use OTP for configuration [default] MIMOPHY_CORE1_ANT0_TX 0 = SROM NOT present [default] 1 PD 1 = SROM present (setting) A A TENDA Title W1800R & W80E Size Document Number Rev B 2.4GHz 4331 RF, XTAL, JTAG, GPIOs 0.1 Date: Tuesday, February 19, 2013 Sheet 15 of 24 5 4 3 2 1

5 4 3 2 1 VDD5_2.4G VDDPA0 VDD3_3 R172 R173 1 2 1 2 RES_1 RES_1 Layout Notes: CAP_4 CAP_4 CAP_4 CAP_4 C564 C540 CAP_4 C538 VDDPA0 RES VDDPA0 CAP_4 CAP_4 If these notes are not followed exactly, then the PAs will perform badly! CAP_4 R174 VCC0_C0 C541 C542 C543 C544 The part placement at the output of the PAs should follow the same T6 structure and orientation as shown on the schematic. All resistors, CAP_4 VDDPA0 VDDPA0 CAP_4 capacitors, and inductors are 0402 size unless otherwise noted. Use the PA_2G_VREF_0 C546 C549 C547 layout of the BCM943222mpgepa or BCM947186nrh boards as a reference. RES_1 CAP_4 1 R175 C545 CAP_4 D C548 C362/C383/C402 should be placed as close to U18/U19/U20 as DFM rules will D CAP_4 allow. The center of the C362/C383/C402 pad should be placed right on the CAP_4 CAP_4 IND CAP_4 2 U28 R1 RES 2 center line of the T1 trace. CAP_4 C554 R176 4 RES_1 2 VCC0 15 EN VCC1 13 1 VCC2 TXG_0 C550 C551 C553 1 RFIN RFOUT1 10 C555 L19 PAOUT_2G_A0 T1: L = 0.97mm (38.0mils), 50ohm impedance 11 RFOUT2 C552 3 5 GND1 GND2 T1 T3 T2 T4 T5 C556 T1 length is measured from the outside edge of the U18/U19/U20 CAP_4 L20 6 9 GND3 GND4 DET 7 DET_2G_0 C560 C557 CRITICAL = Y CAP leads to the long axis center-line of C365/C386/C407. (The center IND C558 C559 12 16 GND5 GND6 NC1 8 CAP_4 point of where the T3 trace joins the T1-T2 trace.) CAP_4 RES_1 L21 17 14 CAP_4 CAP_4 HS-GND NC2 CAP_4 IND SE2605L-QFN16H_8 1 2 R177 TSSI_2G_0 T2: L = 1.7mm (66.9mils), 50ohm impedance 1 C561 R178 C562 T2 length is measured from the long axis center-line of RES_1 CAP_4 C365/C386/C407 (the center point of where the T3 trace joins the Place these parts as close as possible to the 4331(U27) T1-T2 trace) to the center of the C363/C384/C405 land pad. 2 Place C562 close to U17. VDD5_2.4G R179 VDDPA1 R180 VDD3_3 T3: L = 0.94mm (37.2mils), 50ohm impedance 1 2 1 2 RES_1 RES_1 T3 length is measured from the center line of the T1-T2 trace to the center of the C365/C386/C407 land pad. CAP_4 C563 C589 C565 CAP_4 CAP_4 R106/R114/R121 is 0603 size and is placed 1.66mm (65.5mils) away from CAP_4 CAP_4 CAP_4 U18/U19/U20. This dimmension is measured from the outside edge of the CAP_4 VDDPA1 RES VDDPA1 R181 C C VCC0_C1 U18/U19/U20 leads to the long axis center-line of R106/R114/R121. The outer edge of the R106/R114/R121 land pattern should be aligned with CAP_4 C566 C567 C569 C570 T6 CAP_4 VDDPA1 VDDPA1 CAP_4 the center of the T1-T2 trace. C568 C572 C573 PA_2G_VREF_1 RES_1 CAP_4 1 R182 C571 CAP_4 C574 The long axis center line of C366/C387/C408 is centered on the center point of the C363/C384/C405 pad. CAP_4 CAP_4 CAP_4 IND CAP_4 2 U29 R2 RES 2 CAP_4 C578 R183 4 RES_1 2 VCC0 15 EN VCC1 13 1 VCC2 TXG_1 C575 C576 C577 1 RFIN RFOUT1 10 C579 L22 PAOUT_2G_A1 T4: L = 0.94mm (37.2mils), 50ohm impedance 11 RFOUT2 3 5 GND1 GND2 T1 T3 T2 T4 T5 C580 T4 length is measured from the center line of the T5 trace to the C583 6 9 GND3 GND4 DET 7 DET_2G_1 C581 C582 CRITICAL = Y CAP center of the C366/C387/C408 land pad. CAP_4 L23 12 C584 C585 16 GND5 8 CAP_4 GND6 NC1 CAP_4 RES_1 IND 17 14 CAP_4 CAP_4 L24 HS-GND NC2 CAP_4 IND SE2605L-QFN16H_6 1 2 R184 TSSI_2G_1 T5: L = 0.98mm (38.4mils), 50ohm impedance 1 C586 R185 C587 T5 length is measured from the center of the C363/C384/C405 land RES_1 CAP_4 pad to the center of the L9/L12/L15 land pad. 2 Place these parts as close as possible to the 4331(U27) Place C587 close to U17. C364/C385/C406 is placed immediately after L9/L12/L15, as close as VDD5_2.4G R186 VDDPA2 R187 VDD3_3 DFM rules will allow, with it's top land pad directly on the trace B 1 RES_1 2 1 RES_1 2 from L9/L12/L15. B CAP_4 C588 C674 C590 CAP_4 CAP_4 T6: L = 4.7mm (185mils), 50ohm impedance CAP_4 CAP_4 CAP_4 CAP_4 VDDPA2 RES VDDPA2 R188 VCC0_C2 T6 length is measured from the center of the R106/R114/R121 pad to the center of the C357/C378/C399 land pad. CAP_4 C591 C592 C596 C593 T6 CAP_4 VDDPA2 VDDPA2 CAP_4 C359/C380/C401 is placed immediately after R106/R114/R121, as close as PA_2G_VREF_2 C595 C597 C598 DFM rules will allow, with it's top land pad directly on the trace from RES_1 CAP_4 1 R189 C594 C599 CAP_4 R106/R114/R121 to C357/C378/C399. CAP_4 CAP_4 CAP_4 IND CAP_4 2 U30 R3 RES 2 CAP_4 C601 R190 4 RES_1 2 VCC0 15 EN VCC1 13 1 VCC2 C600 C603 C604 1 10 C605 L25 TXG_2 RFIN RFOUT1 PAOUT_2G_A2 11 RFOUT2 3 GND1 T1 T2 T5 C606 C602 5 GND2 T3 T4 6 7 DET_2G_2 CRITICAL = Y CAP_4 L26 9 GND3 DET C609 C610 CAP 12 GND4 IND C607 C608 16 GND5 8 CAP_4 CAP_4 GND6 NC1 CAP_4 RES_1 L27 17 14 CAP_4 CAP_4 HS-GND NC2 IND A R191 A SE2605L-QFN16H_7 1 2 TSSI_2G_2 1 C611 R192 C612 RES_1 CAP_4 Place these parts as close as possible to the 4331(U27) 2 Place C612 close to U17. TENDA Title W1800R & W80E Size Document Number Rev Custom 2.4GHz PAs 0.1 Date: Tuesday, February 19, 2013 Sheet 16 of 24 5 4 3 2 1

5 4 3 2 1 D D VDD3_3 RES_1 IND-DOT-1 RES_1 1 R193 2 L28 VDDLNA_2G_0 1 R194 2 LNA_2G_PU_0 CAP_4 C613 C614 C615 C616 CAP_4 CAP_4 CAP_4 U31 1 6 IND-DOT-1 V_ENABLE VCC CAP_4 LNA_2G_RX0 L29 3 4 C617 LNA_2G_RX0 RF_IN RF_OUT RXG_0 C618 2 C619 C620 GND1 5 CAP_4 GND2 7 CAP_4 CAP_4 HS-GND AMP-SKY65405-QFN6H_7 VDD3_3 RES_1 IND-DOT-1 RES_1 1 R195 2 L30 VDDLNA_2G_1 1 R196 2 LNA_2G_PU_1 CAP_4 C621 C622 C623 C624 C C CAP_4 CAP_4 CAP_4 U32 1 6 IND-DOT-1 V_ENABLE VCC CAP_4 LNA_2G_RX1 L31 3 4 C625 LNA_2G_RX1 RF_IN RF_OUT RXG_1 C627 2 C628 GND1 5 C626 CAP_4 GND2 7 CAP_4 HS-GND CAP_4 AMP-SKY65405-QFN6H_10 VDD3_3 RES_1 IND-DOT-1 RES_1 1 R197 2 L32 VDDLNA_2G_2 1 R198 2 LNA_2G_PU_2 CAP_4 C629 C630 C631 C632 CAP_4 CAP_4 CAP_4 B U33 B 1 6 IND-DOT-1 V_ENABLE VCC CAP_4 LNA_2G_RX2 L33 3 4 C633 LNA_2G_RX2 RF_IN RF_OUT RXG_2 C634 2 C635 C636 GND1 5 CAP_4 GND2 7 CAP_4 CAP_4 HS-GND AMP-SKY65405-QFN6H_11 A A TENDA Title W1800R & W80E Size Document Number Rev C 2.4GHz LNA 0.1 Date: Tuesday, February 19, 2013 Sheet 17 of 24 5 4 3 2 1

5 4 3 2 1 Place the RC filters very close to the RF switch. R199 C0A0TX_2G C0A0TX_2G 1 2 ANT0_2G ANT0_2G C637 R_1 50 PAOUT_2G_A0 1 2 PAOUT_2G_A0 OHMs R200 1 C0A0RX_2G C0A0RX_2G 1 2 C638 CAP_4 R_1 CAP_40 2 2 D D C639 CAP_4 1 1 C640 CAP_40 2 U34 1 6 RF2 V2 2 5 CAP_4 GND RFC 50 LNA_2G_RX0 1 2 3 4 LNA_2G_RX0 RF1 V1 OHMs 2 C641 SKY13377-313 C642 CAP_4 R201 2 C0A0TX_2G 1 2 C0A0TX_2G 2 1 2 L34 R_1 C645 CAP_4 L35 INDUCTOR_3 R202 C0A0RX_2G C0A0RX_2G 1 2 1 1 INDUCTOR_0 R_1 1 Place the RC filters very close to the RF switch. R203 C1A0TX_2G C1A0TX_2G 1 2 R_1 ANT1_2G ANT1_2G R204 C C1A0RX_2G 1 2 C 1 C1A0RX_2G 50 C649 R_1 C648 2 CAP_40 OHMs PAOUT_2G_A1 1 2 C650 2 PAOUT_2G_A1 CAP_4 CAP_4 1 C651 1 CAP_40 2 U35 1 6 RF2 V2 2 5 CAP_4 GND RFC 50 LNA_2G_RX1 1 2 3 4 LNA_2G_RX1 RF1 V1 OHMs C654 2 SKY13377-313 C655 CAP_4 R205 2 C1A0TX_2G 1 2 C1A0TX_2G 2 1 R_1 2 L36 C658 CAP_4 L37 INDUCTOR_3 R206 C1A0RX_2G C1A0RX_2G 1 2 1 1 INDUCTOR_0 R_1 1 Place the RC filters very close to the RF switch. B B R207 C2A0TX_2G C2A0TX_2G 1 2 50 C659 R_1 ANT2_2G ANT2_2G OHMs PAOUT_2G_A2 PAOUT_2G_A2 1 2 R208 CAP_4 C2A0RX_2G 1 2 1 C2A0RX_2G R_1 C660 2 C661 CAP_40 2 CAP_4 1 1 C662 CAP_40 2 U36 1 6 RF2 V2 CAP_4 2 5 50 C665 GND RFC OHMs LNA_2G_RX2 LNA_2G_RX2 1 2 3 RF1 V1 4 2 SKY13377-313 C666 CAP_4 R209 2 C2A0TX_2G 1 2 C2A0TX_2G 2 1 R_1 2 L38 C669 CAP_4 L39 INDUCTOR_3 R210 C2A0RX_2G C2A0RX_2G 1 2 1 1 INDUCTOR_0 R_1 1 Place the RC filters very close to the RF switch. A A TENDA Title W1800R & W80E Size Document Number Rev Custom 2.4GHz Front End 0.1 Date: Tuesday, February 19, 2013 Sheet 18 of 24 5 4 3 2 1

5 4 3 2 1 Pin Chip dafault Board default description 0:20MHz XTAL selected C0_FEMCTRL_1 1 1 1:40MHz XTAL selected PCIE0_RST_L PCIE0_RST_L R211 PCIE_PERST_L RES 0,1:4K SROM size C1_FEMCTRL_0, C0_FEMCTRL_2 0,1 0,1 1,0:16K SROM size 0:don't query OTP C2_FEMCTRL_0 0 0 1:query OTP 0:Boot from SRAM C1_FEMCTRL_1 1 0 U37A 1:Boot from ROM BCM4360KMLG-QFN108H-0.4P D REFCLK_P REFCLK_P REFCLK_N 98 99 REFCLKP SPROM_CS 91 88 C2_FEMCTRL_2 1 1 0:SROM (ATMEL not present if SFLASH is present) D REFCLK_N REFCLKN SPROM_CLK/SECI_AUX 1:SROM present 90 (ST if SFLASH is present) PCIE_TDP 104 SPROM_DIN/SECI_IN 87 PCIE_TDN 103 TDP0 SPROM_DOUT/SECI_OUT TDN0 0:SFLASH not present BANDSEL 0 0 PCIE_0_TDP 106 102 1:SFLASH present PCIE_0_TDP PCIE_0_TDN 107 RDP0 PTESTN 101 VDD3_3 PCIE_0_TDN RDN0 PTESTP PCIE_PERST_L 94 95 PERST_L PCIE_CLKREQ_L gpio[7,6] 1,1 1,1 PCIe:see Twiki R212 97 RES PCIE_PME_L 0:USB 2.0 disable,PCIe enable RF_DISABLE_L 92 gpio8 RF_DISABLE_L (only in 12x12 package) 0 0 1:USB 2.0 enable,PCIe disable (only in 12x12 package) C670 PCIE0_RDP PCIE_TDP PCIE0_RDP CAP PCIE0_RDN C671 PCIE_TDN PCIE0_RDN CAP C672 CAP C673 CAP C C VDD3_3 VDD3_3 VDD3_3 VDD3_3 VDD3_3 R214 R215 R216 R217 R218 U37B RES RES RES RES BCM4360KMLG-QFN108H-0.4P RES 51 8 C0_LNAENA C0_LNAENA 42 RF_2G_IN_CORE0 C0_FEMCTRL_0 9 C0_RX_5G C675 RF_2G_IN_CORE1 C0_FEMCTRL_1 C0_RX_5G 33 11 C0_TX_5G C0_TX_5G RXA_0 49 RF_2G_IN_CORE2 C0_FEMCTRL_2 12 C1_TX_5G RXA_0 RF_5G_IN_CORE0 C1_FEMCTRL_0 C1_TX_5G CAP RXA_1 RXA_1 40 13 C1_RX_5G C1_RX_5G RXA_2 31 RF_5G_IN_CORE1 C1_FEMCTRL_1 15 C1_LNAENA RXA_2 RF_5G_IN_CORE2 C1_FEMCTRL_2 C1_LNAENA 16 C2_TX_5G C2_TX_5G 54 C2_FEMCTRL_0 18 C2_LNAENA RF_2G_OUT_CORE0 C2_FEMCTRL_1 C2_LNAENA 45 19 C2_RX_5G C2_RX_5G 36 RF_2G_OUT_CORE1 C2_FEMCTRL_2 20 C2_LNA_BYPS_5G R226 R219 R220 VDD3_3 VDD3_3 VDD3_3 RF_2G_OUT_CORE2 BANDSEL C2_LNA_BYPS_5G TXA_0 46 more strapping option on gpio6/7 R227 TXA_0 RF_5G_OUT_CORE0 RES RES RES RES RES RES TXA_1 37 TXA_1 RF_5G_OUT_CORE1 RES TXA_2 28 73 PA_VREF TXA_2 RF_5G_OUT_CORE2 O_PAVREF R224 R225 72 PA_5G_VREF_0 R221 R222 O_PAVREF_CTL1 PA_5G_VREF_0 RES RES R223 69 71 PA_5G_VREF_1 TP16 JTAG_TRST_L 64 GPIO_0/TRST_L O_PAVREF_CTL2 70 PA_5G_VREF_2 PA_5G_VREF_1 C676 TP17 JTAG_TDI CAP GPIO_3/TDI O_PAVREF_CTL3 PA_5G_VREF_2 65 TP18 JTAG_TDO 63 GPIO_2/TDO TP19 JTAG_TMS 67 GPIO_4/TMS 24 TSSI_5G_0 TP20 JTAG_TCK 85 GPIO_1/TCK GPAIO_2/TSSI_0 23 TSSI_5G_1 TSSI_5G_0 TP13_UART_RX_4360 83 GPIO_5/EXT_POR_L GPAIO_2/TSSI_1 22 TSSI_5G_2 TSSI_5G_1 GPIO_6/UART_RX GPAIO_2/TSSI_2 TSSI_5G_2 VDD3_3 TP12_UART_TX_4360 82 GPIO_7/UART_TX POPULATE FOR USB 80 VDD3_3 C0_LNA_BYPS_5G 79 GPIO_8 1 C0_LNA_BYPS_5G WLAN_CARD_ACT 78 GPIO_9 MONCDR 2 TP21 B R228 WLAN_CARD_ACT C1_LNA_BYPS_5G C1_LNA_BYPS_5G 77 GPIO_10 GPIO_11 DP DM AVDD3P3 3 4 TP22 R229 B RES 5 RES R230 MONPLL 6 RREF RES C678 C679 CAP CAP 26 84 NC-26 27 JTAG_SEL NC-27 C677 R232 CAP RES 61 R231 XTAL_IN 60 XTAL_OUT TSSI_5G_0 TSSI_5G_0 C680 62 RES R233 XTAL_BUF_OUT CAP TSSI_5G_1 TSSI_5G_1 C681 RES 2 1 CAP Y6 TSSI_5G_2 TSSI_5G_2 C682 Y-SMD CAP C683 CAP 3 4 C684 CAP A A TENDA Title W1800R & W80E Size Document Number Rev A2 5GHz 4360 RF <RevCode> Date: Tuesday, February 19, 2013 Sheet 19 of 24 5 4 3 2 1

5 4 3 2 1 VDD5_5G R234 VDD_PA0 D RES D C685 C686 CAP CAP VDD_PA0 VDD_PA0 VDD_PA0 VDD_PA0 VDD_PA0 C687 C688 C689 C690 C691 C692 C693 CAP CAP CAP CAP CAP CAP CAP C694 R235 R236 PA_5G_VREF_0 PA_5G_VREF_0 R237 RES RES RES CAP R238 C695 RES CAP U39 20 8 VCC1 VCC2_1 19 6 VCC2_2 9 7 SP1 VCC3_1 18 SP2 VCC3_2 R239RES R240 5 10 TSSI_5G_0 TSSI_5G_0 VREF DET L40 C698 C700 RES TXA_0 3 13 TXA_0 RFIN RFOUT C701 C704 L CAP CAP CAP R241 CAP C697 RES C699 R242 C702 1 14 NC GND5 CAP CAP CAP 2 15 RES C703 GND1 GND6 Place 0.3pF shunt capacitor at 4 16 CAP 11 GND2 GND7 17 5mm from edge of PA. GND3 GND8 R243 C709 12 21 L41 GND4 HS_GND RES CAP C C L SE5003L-1_0 L42 C708 L CAP Place 0.1pF shunt capacitor as close to PA output pin as allowed by DRC ANT0_5G ANT0_5G R244 2 C0_LNAENA C0_LNAENA L43 RES C710 CAP_40 1 CAP C711 VDD3_3 CAP U40 6 1 L44 J1 V1 FB18 5 2 GND RFC FB L 4 3 J2 V2 C712 C714 C713 7 CAP CAP L CAP HS_GND CAP SKY13370-374LF_0 L45 C716 U42 6 1 U41 L48 VCC V_ENABLE C721 C722 C717 1 5 4 3 RXA_0 3 VOUT1 IN RF_OUT RF_IN L CAP RXA_0 VOUT2 CAP 2 6 2 R245 GND VCONT1 GND1 C0_RX_5G C0_RX_5G CAP 7 4 5 GND_H VCONT2 GND2 C720 C723 7 RES CAP B C719 sky13351 C718 HS-GND B SKY65404-31 CAP C725 CAP L49 L R246 CAP RES R247 C0_TX_5G C0_TX_5G RES VDD3_3 C726 CAP C727 CAP 5 1 U43 VCC NC R248 C0_LNA_BYPS_5G 2 4 C0_LNA_BYPS_5G A Y GND RES R249 NC7SZ04 3 RES A A TENDA Title W1800R & W80E Size Document Number Rev C Rf Front End-Core 0 <RevCode> Date: Tuesday, February 19, 2013 Sheet 20 of 24 5 4 3 2 1

5 4 3 2 1 VDD5_5G R250 VDD_PA1 D RES D C728 C729 CAP CAP VDD_PA1 VDD_PA1 VDD_PA1 VDD_PA1 VDD_PA1 C730 C731 C732 C733 C734 C735 C736 CAP CAP CAP CAP CAP CAP CAP C737 R251 R252 PA_5G_VREF_1 PA_5G_VREF_1 R253 RES RES RES CAP R254 C738 RES CAP U44 20 8 VCC1 VCC2_1 19 6 VCC2_2 9 7 SP1 VCC3_1 18 SP2 VCC3_2 R255RES R256 5 10 TSSI_5G_1 TSSI_5G_1 VREF DET L50 C740 C744 RES TXA_1 3 13 TXA_1 RFIN RFOUT C747 L CAP CAP C745 R257 CAP C739 RES C742 R258 CAP C743 1 14 NC GND5 CAP CAP CAP 2 15 RES C746 GND1 GND6 Place 0.3pF shunt capacitor at 4 16 CAP 11 GND2 GND7 17 5mm from edge of PA. GND3 GND8 R259 C751 L51 12 21 GND4 HS_GND L RES CAP C C SE5003L-1_0 L52 C752 L CAP Place 0.1pF shunt capacitor as close to PA output pin as allowed by DRC ANT1_5G ANT1_5G R260 2 C1_LNAENA C1_LNAENA L53 RES C753 CAP_40 1 CAP C754 VDD3_3 CAP U45 6 1 L54 J1 V1 FB19 5 2 GND RFC FB L 4 3 J2 V2 C757 C759 C756 7 CAP CAP CAP HS_GND L SKY13370-374LF_0 CAP L55 C758 U47 6 1 U46 L58 VCC V_ENABLE C763 C760 C764 1 5 4 3 RXA_1 3 VOUT1 IN RF_OUT RF_IN L CAP RXA_1 VOUT2 CAP 2 6 2 R261 GND VCONT1 GND1 C1_RX_5G C1_RX_5G CAP 7 4 5 GND_H VCONT2 7 GND2 C765 C766 RES B sky13351 C762 HS-GND B CAP CAP C761 SKY65404-31 CAP C768 CAP CAP RES L59 L R262 R263 C1_TX_5G C1_TX_5G RES VDD3_3 C769 CAP C770 CAP 5 1 U48 VCC NC R264 C1_LNA_BYPS_5G 2 4 C1_LNA_BYPS_5G A Y GND RES R265 NC7SZ04 3 RES A A TENDA Title W1800R & W80E Size Document Number Rf Front End-Core 1 Rev C <RevCode> Date: Tuesday, February 19, 2013 Sheet 21 of 24 5 4 3 2 1

5 4 3 2 1 VDD5_5G R266 VDD_PA2 D RES D C771 C772 CAP CAP VDD_PA2 VDD_PA2 VDD_PA2 VDD_PA2 VDD_PA2 C773 C774 C775 C776 C777 C778 C779 CAP CAP CAP CAP CAP CAP CAP C780 R267 R268 PA_5G_VREF_2 PA_5G_VREF_2 R269 RES RES RES CAP R270 C781 RES CAP U49 20 8 VCC1 VCC2_1 19 6 VCC2_2 9 7 SP1 VCC3_1 18 SP2 VCC3_2 R271RES R272 5 10 TSSI_5G_2 TSSI_5G_2 VREF DET L60 C784 C786 RES TXA_2 3 13 TXA_2 RFIN RFOUT R273 C790 L CAP CAP RES CAP C783 C788 C785 R274 C787 1 14 CAP NC GND5 CAP CAP CAP 2 15 RES C789 GND1 GND6 Place 0.3pF shunt capacitor at 4 16 CAP 11 GND2 GND7 17 5mm from edge of PA. GND3 GND8 R275 C793 12 21 L61 GND4 HS_GND RES CAP C C L SE5003L-1_0 L62 C795 L CAP Place 0.1pF shunt capacitor as close to PA output pin as allowed by DRC ANT2_5G ANT2_5G R276 2 C2_LNAENA C2_LNAENA L63 RES C796 CAP_40 1 CAP C797 VDD3_3 CAP U50 6 1 L64 J1 V1 FB20 5 2 GND RFC FB L 4 3 J2 V2 C799 C801 C802 7 CAP CAP CAP HS_GND L SKY13370-374LF_0 CAP L67 C800 U52 6 1 U51 L68 VCC V_ENABLE C806 C807 C803 1 5 4 3 RXA_2 3 VOUT1 IN RF_OUT RF_IN L CAP RXA_2 VOUT2 CAP 2 6 2 R277 GND VCONT1 GND1 C2_RX_5G C2_RX_5G CAP 7 4 5 GND_H VCONT2 7 GND2 C805 C808 RES B sky13351 C804 HS-GND B CAP CAP C810 SKY65404-31 CAP C811 CAP CAP RES L69 L R278 R279 C2_TX_5G C2_TX_5G RES VDD3_3 C812 CAP C813 CAP 5 1 U53 VCC NC R280 C2_LNA_BYPS_5G 2 4 C2_LNA_BYPS_5G A Y GND RES R281 NC7SZ04 3 RES A A TENDA Title W1800R & W80E Size Document Number Rev C Rf Front End-Core 2 <RevCode> Date: Tuesday, February 19, 2013 Sheet 22 of 24 5 4 3 2 1

5 4 3 2 1 FB FB VDD1_2_RF_5G VDD3_3 VDD1_2_RF_5G VDD1_2_RF_5G U37C VDD3_3 VDD3_3 VDD3_3 Power supply BCM4360KMLG-QFN108H-0.4P decoupling caps CAP CAP CAP CAP CAP CAP CAP CAP FB21 CAP CAP 7 10 FB22 VDD_1 VDDIO_1 C814 C815 14 17 CAP 66 VDD_2 VDDIO_2 68 C816 C817 C818 C819 C820 C821 C822 C823 VDD_3 VDDIO_3 CAP CAP 81 89 86 VDD_4 VDDIO_4 93 VDD_5 VDDIO_5 C148 C132 C356 C168 C149 C357 CAP 96 CAP CAP CAP_4 CAP CAP CAP_4 VDD_6 D D 105 53 PA_2G_CORE0_VDD3P3 100 TVDD PA2G_VDD3P3_CORE0 44 PA_2G_CORE1_VDD3P3 108 PVDD PA2G_VDD3P3_CORE1 35 PA_2G_CORE2_VDD3P3 C824 C825 C826 C827 RVDD PA2G_VDD3P3_CORE2 VDD1P2_GPAIO 25 GPAIO_VDD1P2 47 PA_5G_CORE0_VDD3P3 VDD1_2_CORE0 50 PA5G_VDD3P3_CORE0 38 PA_5G_CORE1_VDD3P3 VDD3_3 VDD3_3 VDD3_3 VDD1_2_RF_5G VDD1_2_CORE1 41 AFERX_VDD1P2_CORE0 PA5G_VDD3P3_CORE1 29 PA_5G_CORE2_VDD3P3 VDD1_2_CORE2 32 AFERX_VDD1P2_CORE1 PA5G_VDD3P3_CORE2 AFERX_VDD1P2_CORE2 CAP CAP CAP CAP CAP CAP CAP CAP RES 48 55 R282 Only one pin per core VDD1_2_5G_0 52 TX5G2G_VDD1P2_CORE0 SYNTH_VDD3P3 76 R283 must be connected. VDD1_2_5G_1 39 TX5G2G_VDD1P2_CORE10_1 VDDPLL C828 C841 TX5G2G_VDD1P2_CORE1 RES C831 C832 C834 C842 C836 The 2 pins per core are shorted 43 C833 insilde the package (leadframe) 30 TX5G2G_VDD1P2_CORE1_1 74 R284 VDD3_3 VDD1_2_5G_2 34 TX5G2G_VDD1P2_CORE2 I_VDD_RFL 75 VDD_RF_LDO TX5G2G_VDD1P2_CORE2_1 O_VDD1P3 RES VDD1P2_LOGEN 56 LOGEN_VDD1P2 21 C845 C835 C846 C839 C829 C830 C840 R285 GPAIO_3/RCAL_EXT_RES CAP CAP CAP CAP CAP CAP CAP 58 VDD1P2_XTAL 59 SYNTH_VDD1P8 RES XTAL_VDD1P2 VDD1P2_XTALF 57 H R286 C837 C843 C838 C844 SYNTHMMD_PFD_VDD1P2 GND_SLUG RES CAP CAP CAP CAP VDD1_2_RF_5G VDD3_3 VDD1_2_RF_5G CAP CAP CAP CAP CAP CAP C847 C848 C849 C850 C851 C852 VDD3_3: PA C C VDD3_3 R287 PA_2G_CORE0_VDD3P3 RES C855 C856 C853 C854 CAP CAP CAP CAP R288 PA_5G_CORE0_VDD3P3 RES VDD1_2: R289 Radio (TX) VDD1_2_5G_0 C857 C858 RES CAP CAP C859 C860 C861 CAP CAP CAP R291 R290 FB23 PA_2G_CORE1_VDD3P3 VDD1P2_XTAL VDD1P2_XTALF VDD1_2_CORE0 RES RES FB C867 C868 C865 C866 C862 VDD_RF_LDO C863 C864 R292 CAP CAP VDD1_2_5G_1 CAP CAP CAP CAP CAP CAP CAP RES Place on top close to pin B C871 C872 B C869 C870 C873 CAP FB24 R293 CAP PA_5G_CORE1_VDD3P3 VDD1_2_CORE1 CAP RES R294 FB VDD_RF_LDO VDD1P2_LOGEN C877 C874 C878 C875 C876 CAP CAP CAP RES CAP Place on top close to pin C879 C880 CAP R295 VDD1_2_5G_2 CAP CAP RES FB25 R296 PA_2G_CORE2_VDD3P3 VDD_RF_LDO VDD1_2_CORE2 C881 C882 C883 RES CAP FB CAP CAP C884 C887 C888 C885 C886 CAP R297 CAP CAP CAP VDD_RF_LDO VDD1P2_GPAIO Place on top close to pin CAP RES C889 C890 CAP CAP R298 PA_5G_CORE2_VDD3P3 RES Implement star connection C891 C892 CAP CAP A A TENDA Title W1800R & W80E Size Document Number Rev A2 <RevCode> 5G PA Power SUPPLY Date: Tuesday, February 19, 2013 Sheet 23 of 24 5 4 3 2 1

5 4 3 2 1 U54 D D ANT2_5G 1 6 CAP_40 ANT2_5G HIGH GND C893 CON4 2 5 2 1 ANT0 1 3 GND COM 50 2 OHMs 2 2 ANT2_2G 3 4 L70 L71 ANT2_2G LOW GND CAP_40 CAP_40 1 1 DP_0 OR??? U55 ANT1_5G 1 6 CAP_40 ANT1_5G HIGH GND C C C894 CON5 2 5 2 1 ANT1 1 3 GND COM 50 2 OHMs 2 2 ANT1_2G 3 4 L72 L73 ANT1_2G LOW GND CAP_40 CAP_40 1 1 DP_0 U56 ANT0_5G 1 6 CAP_40 ANT0_5G HIGH GND C895 CON6 2 5 2 1 ANT2 1 3 B 50 GND COM B OHMs 2 2 2 ANT0_2G 3 4 L74 L75 ANT0_2G LOW GND CAP_40 CAP_40 1 1 DP_0 A A TENDA Title W1800R & W80E Size Document Number Rev B Front End 0.1 Date: Tuesday, February 19, 2013 Sheet 24 of 24 5 4 3 2 1


Document Created: 2013-02-20 09:13:30
Document Modified: 2013-02-20 09:13:30
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