| File Name | Document Type | Date | Direct |
|---|
| request for confidentiality | Cover Letter(s) |
2010-08-06 00:00:00 |
pdf  |
| Authority to act IMQ | Attestation Statements |
2010-08-06 00:00:00 |
pdf |
| photo | Test Setup Photos |
2010-08-06 00:00:00 |
native |
| DETECTOR_DUO user manual | Users Manual |
2010-08-06 00:00:00 |
pdf |
| Test Report | Test Report |
2010-08-06 00:00:00 |
pdf |
| fcc label DETECOR DUO | ID Label/Location Info |
2010-08-06 00:00:00 |
pdf |
| DETECTORDUO fcc_label position | ID Label/Location Info |
2010-08-06 00:00:00 |
pdf |
| DETECTOR_DUO external pictures | External Photos |
2010-08-06 00:00:00 |
pdf |
| DAD external pictures | External Photos |
2010-08-06 00:00:00 |
pdf |
| DAD block diagrams | Block Diagram |
2010-08-06 00:00:00 |
pdf |
| Antenna block diagrams | Block Diagram |
2010-08-06 00:00:00 |
pdf |
| ADC analog to digital conversion circuit | Schematics |
|
N/A |
| ANTENNA internal pictures | Internal Photos |
|
N/A |
| Antenna multiplexer board | Schematics |
|
N/A |
| DAD functional scheme | Schematics |
|
N/A |
| DAD internal pictures | Internal Photos |
|
N/A |
| DAD service interface | Schematics |
|
N/A |
| DETECTORDUO-TECHNICAL DESCRIPTION OF THE UNIT | Operational Description |
|
N/A |
| PC interface LAN - WLAN | Schematics |
|
N/A |
| Power supply high voltage monitor | Schematics |
|
N/A |
| Power supply high voltage section +150 VDC | Schematics |
|
N/A |
| Power supply high voltage section -70 VDC | Schematics |
|
N/A |
| Power supply low voltage section | Schematics |
|
N/A |
| Receiver Board | Schematics |
|
N/A |
| timing circuit | Schematics |
|
N/A |
| timing circuit control ection - CPLD | Schematics |
|
N/A |
| timing circuit control ection - CPU section | Schematics |
|
N/A |
| timing circuit front end | Schematics |
|
N/A |
| timing circuit Static RAM | Schematics |
|
N/A |
| Transmitter Board | Schematics |
|
N/A |
| trigger amplifier board | Schematics |
|
N/A |