Operational Description

FCC ID: SS4BIP5X00

Operational Description

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FCCID_598192

6 Description of Functional Blocks 6.1 RF Receiver The receiver features a near—zero Intermediate Frequency (IF) architecture that allows the channel filters to be integrated on to the die. Sufficient out—of—band blocking specification at the Low Noise Amplifier (LNA) input allows the radio to be used in close proximity to Global System for Mobile Communications (GSM) and Wideband Code Division Multiple Access (W—CDMA) cellular phone transmitters without being desensitised. The use of a digital Frequency Shift Keying (FSK) discriminator means that no discriminator tank is needed and its excellent performance in the presence of noise allows BlueCore3—ROM CSP to exceed the Bluetooth requirements for co—channel and adjacent channel rejection. 6.1.1 Low Noise Amplifier The LNA operates in differential mode and is used for Class 2 operation. 6.1.2 Analogue to Digital Converter \ The Analogue to Digital Converter (ADC)is used to implement fast AutomaticGVaSQntrol(AGC). The ADC samples the Received Signal Strength Indicator (RSS!) voltage on a slot—byélol bastsfl'he front—end LNA gain is changed according to the measured RSSI value, keeplng the first mixer mpufsigqa[\mthln a limited range. This improves the dynamic range of the receiver, improving performance li n [ffiErferencammited environments. \ 6.2 RF Transmitter 6.2.1 1Q Modulator ¢ The transmitter features a direct IQ modulatar to mlwmlse requency drift during a transmit timeslot which results in a controlled modulation index. A digital b s@b\andtnsmlt filter provides the required spectral shaping. & 6.2.2 Power Amplifier \\ \\\\\ The internal Power Amplifier (PA) has\a maxnmumoutput power of +6dBm allowing BlueCore3—ROM CSP to be used in Class 2 and Class 3 radroswm@ external RF PA. X 6.3 RF Syntheslser\\f W > The radio syntheSJsrlswIl nLegrated onto the die with no requirement for an external Voltage Controlled Oscillator (VCO) scre enmg , varactor tuning diodes or LC resonators. The synthesiser is guaranteed to lock in sufficient time acrossthé.guaranteed temperature range to meet the Bluetooth specification V1.2. 6.4 Clock Input and Generation The reference clock for the system is generated from a TCXO or crystal input between 8MHz and 40MHz. All internal reference clocks are generated using a phase locked loop, which is locked to the externalreference frequency.

6.5 Baseband and Logic 6.5.1 Memory Management Unit The Memory Management Unit (MMU) provides a number of dynamically allocated ring buffers that hold the data which is in transit between the host and the air or vice versa. The dynamic allocation of memory ensures efficient use of the available Random Access Memory (RAM) and is performed by hardware MMU to minimise the overheads on the processor during data/voice transfers. 6.5.2 Burst Mode Controller During radio transmission the Burst Mode Controller (BMC) constructs a packet from header information previously loaded into memory—mapped registers by the software and payload data/voice taken from the appropriate ring buffer in the RAM. During radio reception, the BMC stores the packet header in memory—mapped registers and the payload data in the appropriate ring buffer in RAM. This architecture minimises the intervention required by the processor during transmission and reception. 6.5.3 Physical Layer Hardware Engine DSP Dedicated logic is used to perform the following: «_ Forward error correction ® Header error control * Cyclic redundancy check * Encryption * Data whitening «_ Access code correlation * Audio transcoding ® A—law/i—law/linear voice data (frfc}n“{i zy «_ A—law/—law/Continuously V riabl&éis‘!\op * Voice interpolation for\l\q $ 6P : h ( * Rate mismatches ;/”\\ \V ~ eA N p The hardware supgpns‘i\fbp(t@b/a\t and mandatory features of Bluetooth v1.2 including AFH and eSCO. LCX foud 6.5.4 RAM Q/‘ 32Kbytes of on—chip RAM is provided and is shared between the ring buffers used to hold voice/data for each active connection and the general purpose memory required by the Bluetooth stack. 6.5.5 ROM 4Mbits of metal programmable ROM is provided for system firmware implementation. 6.5.6 USB (BC313143A only) This is a full speed Universal Serial Bus (USB) interface for communicating with other compatible digital devices. BlueCore3—ROM CSP acts as a USB peripheral, responding to requests from a master host controller such as a PC.

6.5.7 Synchronous Serial Interface This is a synchronous serial port interface (SP1) for interfacing with other digital devices. The SPI port can be used for system debugging. 6.5.8 UART (BC313141A only) This is a standard Universal Asynchronous Receiver Transmitter (UART) interface for communicating with other serial devices. 6.5.9 Audio PCM Interface The Audio Pulse Code Modulation (PCM) Interface supports continuous transmission and reception of PCM encoded audio data over Bluetooth. 6.6 Microcontroller The microcontroller, interrupt controller and event timer run the Bluetooth software s;ack\and‘centrol the radio and host interfaces. A 16—bit Reduced Instruction Set Computer (RISC) mlcroz;z\vntrollénsy\’for low power consumption and efficient use of memory. § 6.6.1 Programmable 1/O BlueCoreS—ROM CSP has a total of 10 (8 digital and 2 analogue)prgwai‘n%{ e?l/O terminals. These are controlled by firmware running on the device.


Document Created: 2005-10-31 16:17:39
Document Modified: 2005-10-31 16:17:39
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