Block Diagram 2

FCC ID: SJC-ETERNA2

Block Diagram

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FCCID_1866551

                                        ETERNA2 Block Diagram
                                                                                                                               November 1, 2012

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© Dust Networks, Inc. 2012. All Rights Reserved.


1           Block Diagram

                                                                                            32 kHz

                                             Timer Clocks
                                Timers       32.768 kHz &      32 kHz, 20 MHz
                                Sched.
                                                20 MHz
         SRAM                                                     Primary                              Voltage Reference
         72 KB                                                    DC/DC
                                                                 Converter                              Core Regulator

                                                                                                        Clock Regulator
         Flash                  PMU /
                                            Microprocessor              Relaxation                     Analog Regulator
        512 KB                   Clock
                                Control     Clock 1.8432 to              Oscillator




                                                                                                                            20 MHz
                                             18.432 MHz                                  PA
                                                                                       Regulator
        Flash                                                 PoR
       Controller
                                AES             802.15.4
                                                                 DAC          LPF
                                                  Mod
         Code                                                               Tx VCO out = fc MHz               PA
                                                802.15.4                                             PLL
                                Auto
                                                Framing
                                MAC
      Cortex-M3                                   DMA                  Rx VCO out = fc – 2.5 MHz
         System
                                                802.15.4
                                                               ADC Limitter           BPF               PPF     LNA
                                                 Demod

                                                                          AGC
                                                                                        RSSI
           IPCS         CLI         API
                                               ADC            10-bit                                           Bat.
            SPI       UART        UART
                      (2 pin)     (6-pin)      Ctrl.          ADC                                              Load
           Slave                                                              VGA
                                                                                             PTAT
                                                                                               4-bit
                                                                                               DAC

Note that fc = 2405 + n*5 MHz, where n = 0, 1, 2, … 14.




2                                              Dust Networks                                            ETERNA2 Block Diagram



Document Created: 2012-12-04 20:31:38
Document Modified: 2012-12-04 20:31:38

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