Block diagram digital ccts

FCC ID: Q639601

Block Diagram

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FCCID_601724

Commercially confidential Subject: Talladega Short Burst Data Module System Specification Iridium and CCL Use Only Figure 3: Baseband and Digital Block Diagram RTC Power +1V6 +2V5 +2V9 Reset Generator Atmel AT91M55800A MAX6700 RST Real Time Control DACs Clock (10 bit DACs single-ended) VDDBU Control ADCs (10 bit ADCs Call single-ended) Processor Debug UART (ARM7) TI DAC2932 DPL Serial USART 1 Control DACs Interface (for test) (12 bit Auxilliary DACs: SPI Address, single-ended) 4 channels, 12 bits control and 16 bit Parallel data 8MByte Tx DAC TI TMS320VC5416-160 Bus FLASH (12 bit differential) Fs = 2.4MHz Radio System Interface DSP ('C54x) HPI 1MByte SRAM Parallel bus McBSPs S71PL064 module Sync Serial Sync Serial LTC1403A Receiver IF converter ADC (12 bit glue logic and Serial link differential) high rate Fs = 2.4MHz processing Timing control ASIC Data / Fax Synthesizer control Synth and demod Data / Fax Serial Demodulator control control (sync serial) Interface Serial Interface 6.1 Call Processor The call processor (CP), an Atmel AT91M55800A, is the master system processor. It has control of the frame timing: the DSP and all other devices operate as slaves to the CP. The CP device includes not only the processor core, but also the following components in the same part: • 8k byte of static RAM, • a power management controller and clock generator block, • a real time clock (RTC), • a watchdog timer, • an interrupt controller, • three asynchronous serial ports, • a timer-counter block, • an SPI interface, • eight channels of ADC, and C7321-S-002 v1.6 Page 23 of 43 07 September 2005


Document Created: 2019-09-12 10:21:58
Document Modified: 2019-09-12 10:21:58
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