Technical Description

FCC ID: PQN52116TXR2G4

Operational Description

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FCCID_3579400

Technical Description The Equipment Under Test (EUT) is a 2.4GHz Pure Transmitting Controller for RC Robot (Head Unit) operated at 2418-2461MHz with 1MHz Channel Spacing. The EUT is powered by 3 X 1.5V AAA batteries. After switch on the EUT and paired with RC Robot (Head Unit), the RC Robot can be controlled to move forward, backward, turn right/left by the controller. The brief circuit description is listed as below: 1) U24 acts as MCU (GPCE2P064A_DIES). 2) X1 is 32.768kHz crystal oscillator providing clock for U24. 3) U2 acts as 2.4GHz RF Module Circuit (ITR245L). 4) Y1 is 16MHz crystal oscillator providing clock for U2. 5) U4 acts as Voltage Regulator (G5125). 6) U3 acts as Voltage Regulator (LC1218C 3.3V). Antenna Type: Internal antenna Antenna Gain: 0Bi Nominal rated field strength: 92.5dBμV/m at 3m Maximum allowed field strength of production tolerance: +/- 3dB

ITR245L Low Power High Performance 2.4 GHz GFSK Transceiver Features Pin Assignments „ 2400-2483.5 MHz ISM band operation „ Support 250kbps,1Mbps and 2 Mbps air data rate „ Programmable output power „ Low power consumption „ Tolerate +/- 60ppm 16 MHz crystal „ Variable payload length from 1 to 32bytes „ Automatic packet processing „ 6 data pipes for 1:6 star networks „ 2.3V to 3.6V power supply „ 3-pin SPI interface with maximum 6 MHz clock rate „ Compact size Applications „ Wireless PC peripherals „ Wireless mice and keyboards „ Wireless gamepads „ Wireless audio „ VOIP and wireless headsets Block Diagram

ITR245L Table of Contents 1 General Description ................................................................................................................. 3 2 Abbreviations .......................................................................................................................... 4 3 Pin Information ....................................................................................................................... 5 4 State Control ........................................................................................................................... 6 4.1 State Control Diagram ............................................................................................................... 6 4.2 Power Down Mode.................................................................................................................... 7 4.3 Standby-I Mode ......................................................................................................................... 7 4.4 Standby-II Mode........................................................................................................................ 7 4.5 TX Mode ................................................................................................................................... 7 4.6 RX Mode ................................................................................................................................... 8 5 Packet Processing .................................................................................................................... 8 5.1 Packet Format ............................................................................................................................ 8 5.1.1 Preamble........................................................................................................................... 9 5.1.2 Address............................................................................................................................. 9 5.1.3 Packet Control .................................................................................................................. 9 5.1.4 Payload ........................................................................................................................... 10 5.1.5 CRC ................................................................................................................................ 10 5.2 Packet Handling ...................................................................................................................... 10 6 Data and Control Interface .................................................................................................... 11 6.1 TX/RX FIFO ........................................................................................................................... 11 6.2 Interrupt ................................................................................................................................... 11 6.3 SPI Interface ............................................................................................................................ 12 6.3.1 SPI Command ................................................................................................................ 12 6.3.2 SPI Timing ..................................................................................................................... 13 7 Register Map ......................................................................................................................... 14 7.1 Register Bank 0 ....................................................................................................................... 14 7.2 Register Bank 1 ....................................................................................................................... 15 8 Electrical Specifications ......................................................................................................... 16 9 Typical Application Schematic............................................................................................... 18 10 Dimension…………................................................................................................................ 19 11 Order Information ................................................................................................................. 20 12 Update History……. .............................................................................................................. 21 Revision 1.20 Proprietary and Confidential Page 2 of 21

ITR245L Blank page Revision 1.20 Proprietary and Confidential Page 3 of 21

ITR245L 2 Abbreviations ACK Acknowledgement ARC Auto Retransmission Count ARD Auto Retransmission Delay CD Carrier Detection CE Chip Enable CRC Cyclic Redundancy Check CSN Chip Select Not DPL Dynamic Payload Length FIFO First-In-First-Out GFSK Gaussian Frequency Shift Keying GHz Gigahertz LNA Low Noise Amplifier IRQ Interrupt Request ISM Industrial-Scientific-Medical LSB Least Significant Bit MAX_RT Maximum Retransmit Mbps Megabit per second MCU Microcontroller Unit MHz Megahertz MISO Master In Slave Out MOSI Master Out Slave In MSB Most Significant Bit PA Power Amplifier PID Packet Identity Bits PLD Payload PRX Primary RX PTX Primary TX PWD_DWN Power Down PWD_UP Power Up RF_CH Radio Frequency Channel RSSI Received Signal Strength Indicator RX Receive RX_DR Receive Data Ready SCK SPI Clock SPI Serial Peripheral Interface TDD Time Division Duplex TX Transmit TX_DS Transmit Data Sent XTAL Crystal Revision 1.20 Proprietary and Confidential Page 4 of 21

ITR245L 3 Pin Information PIN Name Pin Function Description 1 ANT_I Antenna Antenna connect to main PCB 2 VDD Power Power 3 I CSN Chip select signal 4 I SCK SPI clock 5 I/O DATA Data in/out 6 GND GND System ground 7 ANT Antenna Connect to external antenna Table 1 ITR245L pin functions Revision 1.20 Proprietary and Confidential Page 5 of 21

ITR245L 4 State Control 4.1 State Control Diagram „ Pin signal: VDD, CE ITR245RC has built-in state machines „ SPI register: PWR_UP, PRIM_RX, control the state transition between different EN_AA, NO_ACK, ARC, ARD modes. „ System information: Time out, ACK received, ARD elapsed, ARC_CNT, TX When auto acknowledge feature is disabled, FIFO empty, ACK packet transmitted, state transition will be fully controlled by Packet received MCU. VDD>1.9V Power Down PWR_UP=1 PWR_UP=0 Start up time 1.5ms Standby-I TX FIFO not empty CE=1 for more than 15us Time out or ACK received ARD elapsed and ARC_CNT<ARC TX setting 130us TX finished CE=0 TX FIFO not empty RX CE=1 TX setting 130us TX TX FIFO empty Standby-II CE=1 EN_AA=1 NO_ACK=0 RX setting 130us Figure 3 PTX (PRIM_RX=0) state control diagram Revision 1.20 Proprietary and Confidential Page 6 of 21

ITR245L Figure 4 PRX (PRIM_RX=1) state control diagram 4.2 Power Down Mode 4.4 Standby-II Mode In power down mode ITR245RC is in In standby-II mode more clock buffers are sleep mode with minimal current consumption. active than in standby-I mode and much more SPI interface is still active in this mode, and current is used. Standby-II occurs when CE is all register values are available by SPI. held high on a PTX device with empty TX Power down mode is entered by setting the FIFO. If a new packet is uploaded to the TX PWR_UP bit in the CONFIG register to low. FIFO in this mode, the device will automatically enter TX mode and the packet is transmitted. 4.3 Standby-I Mode By setting the PWR_UP bit in the CONFIG 4.5 TX Mode register to 1 and de-asserting CE to 0, the device enters standby-I mode. Standby-I mode „ PTX device (PRIM_RX=0) is used to minimize average current consumption while maintaining short start-up The TX mode is an active mode where the time. In this mode, part of the crystal oscillator PTX device transmits a packet. To enter this is active. This is also the mode which the mode from power down mode, the PTX device ITR245RC3 returns to from TX or RX mode must have the PWR_UP bit set high, when PRIM_RX bit set low, a payload in the TX CE is set low. FIFO, and a high pulse on the CE for more than 10µs. Revision 1.20 Proprietary and Confidential Page 7 of 21

ITR245L The PTX device stays in TX mode until it high, PRIM_RX bit set high and the CE pin finishes transmitting the current packet. If CE set high. Or PRX device can enter this mode = 0 it returns to standby-I mode. If CE = 1, the from TX mode after transmitting an next action is determined by the status of the acknowledge packet when EN_AA=1 and TX FIFO. If the TX FIFO is not empty the NO_ACK=0 in received packet. PTX device remains in TX mode, transmitting the next packet. If the TX FIFO is empty the In this mode the receiver demodulates the PTX device goes into standby-II mode. It is signals from the RF channel, constantly important to never stay in TX mode for more presenting the demodulated data to the packet than 4ms at one time. processing engine. The packet processing engine continuously searches for a valid If the auto retransmit is enabled (EN_AA=1) packet. If a valid packet is found (by a and auto acknowledge is required matching address and a valid CRC) the (NO_ACK=0), the PTX device will enter TX payload of the packet is presented in a vacant mode from standby-I mode when ARD slot in the RX FIFO. If the RX FIFO is full, elapsed and number of retried is less than the received packet is discarded. ARC. The PRX device remains in RX mode until the „ PRX device (PRIM_RX=1) MCU configures it to standby-I mode or power down mode. The PRX device will enter TX mode from RX mode only when EN_AA=1 and NO_ACK=0 In RX mode a carrier detection (CD) signal is in received packet to transmit acknowledge available. The CD is set to high when a RF packet with pending payload in TX FIFO. signal is detected inside the receiving frequency channel. The internal CD signal is filtered before presented to CD register. The 4.6 RX Mode RF signal must be present for at least 128 µs before the CD is set high. „ PRX device (PRIM_RX=1) „ PTX device (PRIM_RX=0) The RX mode is an active mode where the ITR242C radio is configured to be a receiver. The PTX device will enter RX mode from TX To enter this mode from standby-I mode, the mode only when EN_AA=1 and NO_ACK=0 PRX device must have the PWR_UP bit set to receive acknowledge packet. 5 Packet Processing 5.1 Packet Format The packet format has a preamble, address, packet control, payload and CRC field. Preamble1byte Address3~5byte Packet Control 9/0bit Payload0~32byte CRC2/1byte PayloadLength6bit PID2bit NO_ACK1bit Figure 5 Packet Format Revision 1.20 Proprietary and Confidential Page 8 of 21

ITR245L 5.1.1 Preamble No other data pipe can receive data until a complete packet is received by a data pipe that The preamble is a bit sequence used to detect 0 has detected its address. When multiple PTX and 1 levels in the receiver. The preamble is devices are transmitting to a PRX, the ARD one byte long and is either 01010101 or can be used to skew the auto retransmission so 10101010. If the first bit in the address is 1 the that they only block each other once. preamble is automatically set to 10101010 and if the first bit is 0 the preamble is automatically set to 01010101. This is done to 5.1.3 Packet Control ensure there are enough transitions in the preamble to stabilize the receiver. When Dynamic Payload Length function is enabled, the packet control field contains a 6 bit payload length field, a 2 bit PID (Packet 5.1.2 Address Identity) field and, a 1 bit NO_ACK flag. This is the address for the receiver. An address „ Payload length ensures that the packet is detected by the target The payload length field is only used if the receiver. The address field can be configured Dynamic Payload Length function is enabled. to be 3, 4, or 5 bytes long by the AW register. „ PID The PRX device can open up to six data pipes The 2 bit PID field is used to detect whether to support up to six PTX devices with unique the received packet is new or retransmitted. addresses. All six PTX device addresses are PID prevents the PRX device from presenting searched simultaneously. In PRX side, the data the same payload more than once to the MCU. pipes are enabled with the bits in the The PID field is incremented at the TX side EN_RXADDR register. By default only data for each new packet received through the SPI. pipe 0 and 1 are enabled. The PID and CRC fields are used by the PRX device to determine whether a packet is old or Each data pipe address is configured in the new. When several data packets are lost on the RX_ADDR_PX registers. link, the PID fields may become equal to the last received PID. If a packet has the same PID Each pipe can have up to 5 bytes configurable as the previous packet, ITR242C compares the address. Data pipe 0 has a unique 5 byte CRC sums from both packets. If the CRC address. Data pipes 1-5 share the 4 most sums are also equal, the last received packet is significant address bytes. The LSB byte must considered a copy of the previously received be unique for all 6 pipes. packet and discarded. „ NO_ACK To ensure that the ACK packet from the PRX is transmitted to the correct PTX, the PRX The NO_ACK flag is only used when the auto takes the data pipe address where it received acknowledgement feature is used. Setting the the packet and uses it as the TX address when flag high, tells the receiver that the packet is transmitting the ACK packet. not to be auto acknowledged. On the PRX, the RX_ADDR_Pn, defined as The PTX can set the NO_ACK flag bit in the the pipe address, must be unique. On the PTX Packet Control Field with the command: the TX_ADDR must be the same as the W_TX_PAYLOAD_NOACK. However, the RX_ADDR_P0 on the PTX, and as the pipe function must first be enabled in the address for the designated pipe on the PRX. FEATURE register by setting the Revision 1.20 Proprietary and Confidential Page 9 of 21

ITR245L EN_DYN_ACK bit. When you use this option, 5.1.5 CRC the PTX goes directly to standby-I mode after transmitting the packet and the PRX does not The CRC is the error detection mechanism in transmit an ACK packet when it receives the the packet. The number of bytes in the CRC is packet. set by the CRCO bit in the CONFIG register. It may be either 1 or 2 bytes and is calculated 5.1.4 Payload over the address, Packet Control Field, and Payload. The payload is the user defined content of the packet. It can be 0 to 32 bytes wide, and it is The polynomial for 1 byte CRC is X8 + X2 + transmitted on-air as it is uploaded X + 1. Initial value is 0xFF. (unmodified) to the device. The polynomial for 2 byte CRC is X16 + X12 + X5 + 1. Initial value is 0xFFFF. The ITR242C provides two alternatives for handling payload lengths, static and dynamic No packet is accepted by receiver side if the payload length. The static payload length of CRC fails. each of six data pipes can be individually set. The default alternative is static payload length. 5.2 Packet Handling With static payload length all packets between a transmitter and a receiver have the same ITR242C uses burst mode for payload length. Static payload length is set by the transmission and receive. RX_PW_Px registers. The payload length on the transmitter side is set by the number of The transmitter fetches payload from TX FIFO, bytes clocked into the TX_FIFO and must automatically assembles it into packet and equal the value in the RX_PW_Px register on transmits the packet in a very short burst the receiver side. Each pipe has its own period with 1Mbps or 2Mbps air data rate. payload length. After transmission, if the PTX packet has the Dynamic Payload Length (DPL) is an NO_ACK flag set, ITR242C sets TX_DS and alternative to static payload length. DPL gives an active low interrupt IRQ to MCU. If enables the transmitter to send packets with the PTX is ACK packet, the PTX needs variable payload length to the receiver. This receive ACK from the PRX and then asserts means for a system with different payload the TX_DS IRQ. lengths it is not necessary to scale the packet length to the longest payload. The receiver automatically validates and disassembles received packet, if there is a With DPL feature the ITR242C can decode the valid packet within the new payload, it will payload length of the received packet write the payload into RX FIFO, set RX_DR automatically instead of using the RX_PW_Px and give an active low interrupt IRQ to MCU. registers. The MCU can read the length of the received payload by using the command: When auto acknowledge is enabled R_RX_PL_WID. (EN_AA=1), the PTX device will automatically wait for acknowledge packet In order to enable DPL the EN_DPL bit in the after transmission, and re-transmit original FEATURE register must be set. In RX mode packet with the delay of ARD until an the DYNPD register has to be set. A PTX that acknowledge packet is received or the number transmits to a PRX with DPL enabled must of re-transmission exceeds a threshold ARC. If have the DPL_P0 bit in DYNPD set. the later one happens, ITR242C will set MAX_RT and give an active low interrupt Revision 1.20 Proprietary and Confidential Page 10 of 21

ITR245L IRQ to MCU. Two packet loss counters accessible through the SPI by using dedicated (ARC_CNT and PLOS_CNT) are incremented SPI commands. A TX FIFO in PRX can store each time a packet is lost. The ARC_CNT payload for ACK packets to three different counts the number of retransmissions for the PTX devices. If the TX FIFO contains more current transaction. The PLOS_CNT counts than one payload to a pipe, payloads are the total number of retransmissions since the handled using the first in first out principle. last channel change. ARC_CNT is reset by The TX FIFO in a PRX is blocked if all initiating a new transaction. PLOS_CNT is pending payloads are addressed to pipes where reset by writing to the RF_CH register. It is the link to the PTX is lost. In this case, the possible to use the information in the MCU can flush the TX FIFO by using the OBSERVE_TX register to make an overall FLUSH_TX command. assessment of the channel quality. The RX FIFO in PRX may contain payload The PTX device will retransmit if its RX FIFO from up to three different PTX devices. is full but received ACK frame has payload. . A TX FIFO in PTX can have up to three As an alternative for PTX device to auto payloads stored. retransmit it is possible to manually set the ITR242C to retransmit a packet a number of The TX FIFO can be written to by three times. This is done by the REUSE_TX_PL commands, W_TX_PAYLOAD and command. W_TX_PAYLOAD_NO_ACK in PTX mode and W_ACK_PAYLOAD in PRX mode. All When auto acknowledge is enabled, the PRX three commands give access to the TX_PLD device will automatically check the NO_ACK register. field in received packet, and if NO_ACK=0, it will automatically send an acknowledge The RX FIFO can be read by the command packet to PTX device. If EN_ACK_PAY is set, R_RX_PAYLOAD in both PTX and PRX and the acknowledge packet can also include mode. This command gives access to the pending payload in TX FIFO. RX_PLD register. The payload in TX FIFO in a PTX is NOT removed if the MAX_RT IRQ is asserted. 6 Data and Control Interface In the FIFO_STATUS register it is possible to 6.1 TX/RX FIFO read if the TX and RX FIFO are full or empty. The TX_REUSE bit is also available in the The data FIFOs are used to store payload that FIFO_STATUS register. TX_REUSE is set by is to be transmitted (TX FIFO) or payload that the SPI command REUSE_TX_PL, and is is received and ready to be clocked out (RX reset by the SPI command: FIFO). The FIFO is accessible in both PTX W_TX_PAYLOAD or FLUSH TX. mode and PRX mode. 6.2 Interrupt There are three levels 32 bytes FIFO for both TX and RX, supporting both acknowledge In ITR242C there is an active low interrupt mode or no acknowledge mode with up to six (IRQ) pin, which is activated when TX_DS pipes. IRQ, RX_DR IRQ or MAX_RT IRQ are set „ TX three levels, 32 byte FIFO high by the state machine in the STATUS „ RX three levels, 32 byte FIFO register. The IRQ pin resets when MCU writes '1' to the IRQ source bit in the STATUS Both FIFOs have a controller and are register. The IRQ mask in the CONFIG Revision 1.20 Proprietary and Confidential Page 11 of 21

ITR245L register is used to select the IRQ sources that to low transition on CSN. are allowed to assert the IRQ pin. By setting one of the MASK bits high, the corresponding In parallel to the SPI command word applied IRQ source is disabled. By default all IRQ on the MOSI pin, the STATUS register is sources are enabled. shifted serially out on the MISO pin. The 3 bit pipe information in the STATUS The serial shifting SPI commands is in the register is updated during the IRQ pin high to following format: low transition. If the STATUS register is read during an IRQ pin high to low transition, the „ <Command word: MSB bit to LSB bit pipe information is unreliable. (one byte)> „ <Data bytes: LSB byte to MSB byte, MSB bit in each byte first> for all 6.3 SPI Interface registers at bank 0 and register 9 to register 14 at bank 1 6.3.1 SPI Command „ <Data bytes: MSB byte to LSB byte, MSB bit in each byte first> for register 0 to register 8 at bank 1 The SPI commands are shown in Table 2. Every new command must be started by a high Command # Data Command name word Operation bytes (binary) 1 to 5 Read command and status registers. AAAAA = R_REGISTER 000A AAAA 5 bit Register Map Address LSB byte first Write command and status registers. AAAAA = 5 1 to 5 bit Register Map Address W_REGISTER 001A AAAA LSB byte first Executable in power down or standby modes only. Read RX-payload: 1 – 32 bytes. A read operation 1 to 32 always starts at byte 0. Payload is deleted from FIFO R_RX_PAYLOAD 0110 0001 LSB byte first after it is read. Used in RX mode. 1 to 32 Write TX-payload: 1 – 32 bytes. A write operation W_TX_PAYLOAD 1010 0000 always starts at byte 0 used in TX payload. LSB byte first FLUSH_TX 1110 0001 0 Flush TX FIFO, used in TX mode Flush RX FIFO, used in RX mode Should not be executed during transmission of FLUSH_RX 1110 0010 0 acknowledge, that is, acknowledge package will not be completed. Used for a PTX device Reuse last transmitted payload. Packets are repeatedly retransmitted as long as CE is high. TX payload reuse is active until REUSE_TX_PL 1110 0011 0 W_TX_PAYLOAD or FLUSH TX is executed. TX payload reuse must not be activated or deactivated during package transmission Revision 1.20 Proprietary and Confidential Page 12 of 21

ITR245L This write command followed by data 0x73 activates the following features: • R_RX_PL_WID • W_ACK_PAYLOAD • W_TX_PAYLOAD_NOACK A new ACTIVATE command with the same data deactivates them again. This is executable in power down or stand by modes only. The R_RX_PL_WID, W_ACK_PAYLOAD, and ACTIVATE 0101 0000 1 W_TX_PAYLOAD_NOACK features registers are initially in a deactivated state; a write has no effect, a read only results in zeros on MISO. To activate these registers, use the ACTIVATE command followed by data 0x73. Then they can be accessed as any other register. Use the same command and data to deactivate the registers again. This write command followed by data 0x53 toggles the register bank, and the current register bank number can be read out from REG7 [7] Read RX-payload width for the top R_RX_PL_WID 0110 0000 R_RX_PAYLOAD in the RX FIFO. Used in RX mode. Write Payload to be transmitted together with ACK packet on PIPE PPP. (PPP valid in the range from 000 1 to 32 to 101). Maximum three ACK packet payloads can be W_ACK_PAYLOAD 1010 1PPP pending. Payloads with same PPP are handled using LSB byte first first in - first out principle. Write payload: 1– 32 bytes. A write operation always starts at byte 0. W_TX_PAYLOAD_NO 1 to 32 Used in TX mode. Disables AUTOACK on this 1011 0000 specific packet. ACK LSB byte first No Operation. Might be used to read the STATUS NOP 1111 1111 0 register Table 2 SPI command Revision 1.20 Proprietary and Confidential Page 13 of 21

ITR245L 7 Register Map Address Register BIT Recommend R/W Description （HEX） 0 CONFIG Operation Register DATAOUT_S 7 0 R/W EL MASK_RX_D 6 0 R/W R MASK_TX_D 5 0 R/W S MASK_MAX_ 4 0 R/W RT EN_CRC 3 1 R/W CRC Eanble 1: CRC enable，2byte 0: CRC disable，no CRC Checksum N/A 2 0 R/W Reserve PWR_UP 1 0 R/W Chip enable 1: POWER_UP 0: POWER_DOWN PRIM_RX 0 0 R/W RX/TX control 1: PRX 0: PTX Revision 1.20 Proprietary and Confidential Page 14 of 21

ITR245L 1 EN_AA Auto ACK Enhanced Burst Reserved 7:6 0 R/W Only 00 allowed ENAA_P5 5 0 R/W Enable pipe5 auto ACK ENAA_P4 4 0 R/W Enable pipe4 auto ACK ENAA_P3 3 0 R/W Enable pipe3 auto ACK ENAA_P2 2 0 R/W Enable pipe2 auto ACK ENAA_P1 1 0 R/W Enable pipe1 auto ACK ENAA_P0 0 1 R/W Enable pipe0 auto ACK 2 EN_RXADDR Receive channel enable Reserved 7:6 0 R/W Only 00 allowed ERX_P5 5 0 R/W Enable data pipe 5 ERX_P4 4 0 R/W Enable data pipe 4 ERX_P3 3 0 R/W Enable data pipe 3 ERX_P2 2 0 R/W Enable data pipe 2 ERX_P1 1 0 R/W Enable data pipe 1 ERX_P0 0 1 R/W Enable data pipe 0 3 SETUP_AW Address setting Reserved 7:2 0 R/W Only 000000 allowed AW 1:0 11 R/W RX/TX Address width 00: 01: 3 Byte 10: 4 Byte 11: 5 Byte 4 SETUP_RETR Auto transmission setting Revision 1.20 Proprietary and Confidential Page 15 of 21

ITR245L ARD 7:4 0 R/W Auto delay timing 0000 :250µs 0001 :500µs 0010 :750µs …… 1111: 4000µs ARC 3:0 11 R/W Auto retry count 8 Electrical RF characteristic Characteristic VCC = 3V± Value Unit 5%， TA=25℃) Min Typical Max ICC Sleep 2 uA Standby I 50 uA Standby Ⅱ 750 uA TX (0dBm) 15 16 mA TX (8dBm) 23 25 mA RX (2Mbps) 15 16 mA RX (1Mbps) 14 15 mA fOP Operation frequency 2400 2483 MHz PLLres Phase lock loop step １ MHz f XTAL Crystal 16 MHz DR Bit rate 1 2 Mbps ∆f1M Frequency Delta@1Mbps 160 250 KHz ∆f 2 M Frequency Delt@2Mbps 320 500 KHz FCH 1M Channel space @1Mbps 1 MHz FCH 2 M Channel space @2Mbps 2 MHz TX PRF Typical power 1 8 dBm PRF Typical power 2 0 dBm PRFC Output power range -11 11 dBm Revision 1.20 Proprietary and Confidential Page 16 of 21

ITR245L PBW 2 CW 20dB bandwidth（2Mbps） 1.8 2.1 MHz PBW1 CW 20dB bandwidth (1Mbps) 0.9 1.1 MHz RX RX max Bit error rate <0.1%@RX max 0 dBm RXSENS 2 RX sensistivity（0.1%BER） -85 dBm @2Mbps RXSENS1 RX sensistivity（0.1%BER） -88 dBm @1Mbps C / Ι CO C / Ι CO @2Mbps 13 dBc C / Ι1ST C / Ι1ST @2Mbps -8 dBc C / Ι2 ND C / Ι2 ND @2Mbps -12 dBc C / Ι 3 RD C / Ι 3 RD @2Mbps -20 dBc C / Ι4TH C / Ι4TH @2Mbps -28 dBc C / Ι CO C / Ι CO @1Mbps 13 dBc C / Ι1ST C / Ι1ST @1Mbps 5 dBc C / Ι2 ND C / Ι2 ND @1Mbps -10 dBc C / Ι 3 RD C / Ι 3 RD @1Mbps -16 dBc C / Ι4TH C / Ι4TH @1Mbps -24 dBc Operation VDD Supply voltage 2.2 3 3.6 V VSS GND 0 V VOH High output VDD-0.3 VDD V VOL Low ouput VSS VSS+0.3 V VIH High input 2 3 3.6 V VIL Low input VSS VSS+0.3 V TOP Operation temperature 0 70 ℃ TSTG Storage Temperature -20 85 ℃ Revision 1.20 Proprietary and Confidential Page 17 of 21

ITR245L 9 Dimension PCB SIZE: 14x 16mm Pitch: 2.00 mm Tolerence: 0.2mm Revision 1.20 Proprietary and Confidential Page 18 of 21

ITR245L 10 Order Information . ITR245XX-V YYYY Z XX :L YYYY : Customer code Z : T = TX , R = RX Eg. ITR245L Revision 1.20 Proprietary and Confidential Page 19 of 21

ITR245L 11 Update History Ver. Date Description 1.0 Jan,2014 New Release 1.1 Oct,2014 Update the dimension 1.11 Jan 2015 Update dimension 1.20 AUG2015 New release for SOP8 version Revision 1.20 Proprietary and Confidential Page 20 of 21

ITR245L Zittec Technology Incorporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design orperformance and to supply the best possible product. Zittec Technology does not assume any responsibility for use of any circuitry described other than thecircuitry embodied in Zittec Semiconductor Technology product. The company makes no representations that circuitry described herein is free from patent infringement or otherrights, of Zittec Technology Incorporation Revision 1.20 Proprietary and Confidential Page 21 of 21


Document Created: 2017-07-27 14:47:16
Document Modified: 2017-07-27 14:47:16
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