Description

FCC ID: KBCIX260-PROAC555

Operational Description

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FCCID_453790

                 1XRTT AC555 Detailed
                        Circuit Description
                       Document #:                 2110622
                          Revision:                   C




                            ? 1999-2001 Sierra Wireless Inc.
The contents of this page are subject to the confidentiality information on page one.


                                            SIERRA WIRELESS INC.

    Document #:                2110622                         Revision:            C                  Page 2 of 14

Table of Contents

1      General ..................................................................................................3
    1.1       Purpose ........................................................................................................... 3
    1.2       Scope............................................................................................................... 3
    1.3       Glossary of terms............................................................................................. 3
    1.4       References ....................................................................................................... 3
    1.5       Revision history ............................................................................................... 3
2      Circuit Description .................................................................................4
    2.1    LOGIC ............................................................................................................ 4
      2.1.1   Block Diagram......................................................................................... 4
      2.1.2   MSM5105................................................................................................ 4
      2.1.3   FPGA/ASIC............................................................................................. 5
      2.1.4   DC to DC Converter ................................................................................ 6
      2.1.5   Voltage Regulators................................................................................... 6
      2.1.6   Audio Circuitry ........................................................................................ 6
3      Aircard 555 Radio ..................................................................................7
    3.1    RF Circuit, Cellular and PCS Transceiver....................................................... 7
    3.2    Specifications .................................................................................................. 7
    3.3    Architecture..................................................................................................... 9
    3.4    Frequency Generation Unit ........................................................................... 11
      3.4.1    19.2 MHz Reference Oscillator .............................................................. 11
      3.4.2    LO Buffer Amplifiers............................................................................. 11
    3.5    Transmitter.................................................................................................... 11
      3.5.1    Power Amplifier .................................................................................... 12
      3.5.2    Automatic level control.......................................................................... 12
      3.5.3    Duplexer and Diplexer ........................................................................... 12
    3.6    Receiver......................................................................................................... 12
    3.7    Baseband Audio Processing – Transmitter and Receiver ............................... 13
    3.8    Tuning Functions........................................................................................... 13
      3.8.1    TRK_LO_ADJ....................................................................................... 13
      3.8.2    PA_ON_PCS, PA_ON_CELL ............................................................... 13
      3.8.3    TX_AGC_ADJ ...................................................................................... 13
      3.8.4    I_OFFSET, Q_OFFSET......................................................................... 13
      3.8.5    SY_SENDB, SY_SDATA, SY_SCLK................................................... 13
      3.8.6    SBCK, SBST, SBDT ............................................................................. 14
    3.9    Power Supply................................................................................................. 14




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                                  SIERRA WIRELESS INC.

      Document #:      2110622               Revision:     C            Page 3 of 14



1      General

1.1     Purpose

This document details the logic circuitry of the AC555 modems.

1.2     Scope

This document covers only the logic portion of the product.

1.3     Glossary of terms

1XRTT – Qualcomm’s CDMA2000 Standard.
ASIC – Application-Specific Integrated Circuit
FPGA – Field Programmable Gate Array
PCMCIA – Personal Computer Memory Card International Association
PWM – Pulse Width Modulated
TCXO – Temperature Controlled Oscillator
USB – Universal Serial Bus

1.4     References

Ref. #       Doc. #               Document title
R-1                               MSM5105 Device Specification
R-2                               RFT3100 Device Specification
R-3                               IFR3000 Device Specification

1.5     Revision history

Revision  Date           Author                  Summary of changes                 ECO #
A        Nov 24,       Phillips       Original
         2000
B        Dec 7,        Phillips       Modified document based on feedback.
         2000
C        Aug 2,        D. Kwong       Added RF section
         2001          T. McKeen




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      Document #:      2110622                   Revision:          C        Page 4 of 14


2      Circuit Description

2.1     LOGIC

2.1.1 Block Diagram

                                                            CWE                                     Bypass
                                                                                                    Circuit
                                                             3.3V
                                                  Radio
                                                 Voltages
                                                                                       Regulators   Voltage
                                                                        2.5V/3.0V                   Detector
                                RX I Data (4)
                                RX Q Data (4)


                               RX_AGC_ADJ
                                                                             FLASH/RAM
                                                                                          2.5V/
                    IFR3000      I_OFFSET                                   16M/4M - 16 Bit3.0V     DC/DC
                                 Q_OFFSET
                                 SLEEP_N                                     (soft NVRAM)
                               LNA_RANGE0
                               LNA_RANGE1
                                Serial Bus (3)


                                                                                      NDIS          P
         Radio                                                                                      C
                                 TCXO                                                               M
                    TCXO       TRK_LO_ADJ             MSM5105                       X ilinx FPGA
                              TCXO_ENABLE                                                           C
                                                                                         CIS        I
                                                                                                    A
                                                                                      16550
                                TX I Signal
                               TX I Signal_N
                                TX Q Signal                                                         LED
                               TX Q Signal_N
                    RFT3100    TX_AGC_ADJ
                               SYNTH_LOCK
                                 IDLE_N
                                 PA_ON                                      Audio                    Audio
                                  PA_R0
                                  PA_R1                                   Conditioning              Connector




2.1.2 M S M 5 1 0 5

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                                    SIERRA WIRELESS INC.

   Document #:            2110622                  Revision:        C              P a g e5 o f 1 4

T h e M S M 5 1 0 5 i s a Q u a lco m m ’s A S I C . I t ’s the lower                n ocost
                                                                                          f theversio
                                                                                                  MSM5100.
B o t h c h i p s a r e t h e 1 X R T T v e r s i o n o f t h e M S M 3 1 0 0 . T h e M S M 3 1 0 0 is not compatible
w ith the M S M 3 0 0 0 , w h i c h w e u s e d o n t h e A irC a r d 5 1 0 . T h e M S M 5 1 0 5 c o n t a i n s a n
A R M 7 m icro controller, a D S-c           P ,h aann n8e l A / D c o n v e r t e r , v o i c e c o d e c , 1 ,U2S B p o r t
U A R T p o rts, and some other glue logic.

T h e M S M 5 1 0 5 u s e s t h e F L A S H t o s t o r e i t s f i r m w a r e a n d t h e R A M to store variables.
The FLASH and RAM are combined in one stacked chip part. This type of part was
c h o s e n t o s a v e s p a c e o n t h e P C B . T h e F LsAuSp H        p owr t ill“read w h ile w r ite” operation,
w h ich allow s t h e d a t a t h a t u s e d t o b e s t o r e d i n t h e e x t e r n a l E E P R O M t o m o v e i n t o t h e
F L A S H . T h e F L A S H R O M h a s 1 6 M e g a b its of storage arranged in 2M b y 1 6 b it w o r d s .
T h e F L A S H is sectorized so that it can bederased                  p r o g r aanmmed in blocks. The RAM
is a 4 M e g a b i t p a r t a r r a n g e d i n 2 5 6 k b y 8 1 6 b i t w o r d s . O n e q u a r t e r o f t h e F L A S H i s
r e s e r v e d t o r e p l a c e t h e f u n c t i o n o f t h e E E P R O M . The special bank can also store data
s u c h a s t h e C I S a n d F P G A p r o g r a m m i n g i n f o r misa t not   i o n used
                                                                                          that when the CDM A
engine is running.

T h e M S M 5 1 0 5 r u n s o f f the radio’s 1 9 . 6 8 M H z T C X O c lock. It has a secondary
32.768kHz clock, which it uses when in sleep mode to wake up the TCXO clock.

T h e M S M 3 0 0 0 h a s t w o i n t e r f a c e s t o o t h e r p a r t su oit.f t The
                                                                                     h e c ifirst
                                                                                             r c is the interface to
t h e F P G A / A S I C . T h e F P G A / A S I C is attached to the M S M 5 1 0 5 t h r o u g h its m e m o r y b u
This allow s t h e F P G A / A S I C t o b e p a r t o f t h e M S M 5 1 0 5 ’s m e m o r y m a p . T h e s e c o n d
interface is to the radio. The transm it and receive                      are signals
                                                                                  sent from the M S M 5 1 0 5 ’s
DSP to the radio as I and Q data. The receive data is digital but the transmit data is
analog. This is different from the A irC a r d 5 1 0 , w h i c h w a s e n t i r e l y d i g i t a l . T h e o t h e r
control signals are on/off signals such as thel i nPA_O                 e a n dNP W M signals such as
T X _ A G C _ A D J. PW M signals once properly filter can server as D / A o u t p u t s .


2.1.3 F P G A /A S I C

The logic interface chip is an FPG A d u r i n g d e v e l o p m e n t a n d A S I C d u r i n g p r o d u c t i o n . I
s e r v e s t h e p u r p o s e o f P C M C I A i n t e r f a c e . T h e Pterface
                                                                            CM C I A
                                                                                   allow
                                                                                      in s t h e m o d e m t o
b e p l u g g e d i n t o a n d p o w e r e d o n i n a n y P C M C I A s o c k e t . T h e F P G A / A S I C p r o v ides the
CIS information the PCMCIA host needs. This information is programmed into the
A S I C b y t h e M S M 5 1 0 5 u p o n b o o t u p . T h e F P G A / A S I C a l s o550   c o nserial
                                                                                                 t a i n s port
                                                                                                           a 16
emulator and an NDIS interface w ith dual 256 by 16bit synchronous FIFOs. The 16550
port is for FAX and circuit sw i t c h e d c o n n e c t i o n s . T h e N D I S i s f o r p a c k e t c o n n e c t i o n s
and status information.




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                               SIERRA WIRELESS INC.

   Document #:        2110622               Revision:      C            Page 6 of 14



2.1.4   DC to DC Converter

The modem has one DC-to-DC converter, which is uses to convert 5.0V down to 3.3V.
This allows the modem to work in both 5.0V and 3.3V PCMCIA sockets. It is capable of
delivering 1Amp of continuous current at an efficiency of over 90%. There is a voltage
detector, which senses if the input voltage is 3.3V. If it is, then the DC/DC converter is
switched off and the bypass FET is switched on.


2.1.5   Voltage Regulators

The modem has multiple low-dropout regulators. One is used to power the MSM5105
and the Xilinx FPGA. The others are there to provide various voltages to the radio. The
regulators also have the addition functions of providing isolation and volt-dip protection.


2.1.6   Audio Circuitry

The AirCard555 is capable of doing voice calls. For this reason connections are made to
the MSM5105’s built-in codec to provide microphone input and speaker output on the
audio connector.




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                               SIERRA WIRELESS INC.

      Document #:        2110622             Revision:     C            Page 7 of 14


3      Aircard 555 Radio


3.1     RF Circuit, Cellular and PCS Transceiver

The transceiver is a spread spectrum O-QPSK full duplex modem capable of operating in
the AMPS (824 – 894 MHz) and PCS (1850 – 1990 MHz) bands. Max output power is
+23.0 dBm as outlined in the IS2000 and IS-98D CDMA standard with a max current
draw of 800 mA while transmitting at this level. Channel spacing for the above bands is
30 KHz for AMPS and 50 KHz for PCS.


3.2     Specifications

Aircard 555 will comply with the requirements of IS-2000 and IS-98-D.


General

Table 1:         Power Supply

      DC Power Supply                3.3V +/- 5% in series with a source impedance of 0.5 ohms
                                                  (minimum of 3.0V under load)


Table 2: Transceiver Specifications


                                                                AMPS                       PCS
                Transmit Frequency                        824 to 848 MHz            1850 to 1910 MHz
                 Receive Frequency                        869 to 893 MHz            1930 to 1990 MHz
                  Channel Spacing                              30 KHz                    50 KHz
                      Modes                                      Receive, Full Duplex Transmit
                    Modulation                                     O-QPSK, BW = 1.25MHz
              Performance Bandwidth                            25 MHz                    60 MHz
                Frequency Stability                      +/- 2.5 ppm over all environmental conditions
                   Transmitter
         Transmit Output Power (conducted)               200 mW (23 dBm), adjustable to .010 uW (-50
                                                                     dBm) @ +3.3Vdc
            Transmitter Spurious Outputs                            Per FCC Part 22, 24



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   Document #:       2110622               Revision:     C            Page 8 of 14

                    Receiver
             Sensitivity (conducted)                          -104 dBm for 1% FER (AMPS)
                                                               -104 dBm for 1% FER (PCS)
                    ACPR
                     PCS                                           -42 dBc @ 1.25MHz
                    AMPS                                            -42 dBc @ 885KHz
              Spurious Emissions                                        Per FCC 15


Table 4: Environmental Specifications

The product must, as a minimum, meet all PCMCIA specifications (release 2.01, section
3.6) except for operating temperatures as shown below:

             Operation Temperature                                  -30 to +65 deg. C
                   Humidity                                        95% non-condensing
                   Vibration                                        Per PCMCIA spec
                                                          15G peak, 10-2000 Hz (non-operating)
                      ESD                                           Per PCMCIA spec
                     Shock                                          Per PCMCIA spec
                     Drop                           30 in. onto non-cushioning vinyl covered concrete


Physical Specifications

Aircard 555 will be a type II PCMCIA card with minimal (<15mm) or no extension other
than the antenna.




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                               SIERRA WIRELESS INC.

      Document #:      2110622              Revision:      C           Page 9 of 14

Antenna Specifications

The antenna is a removable hinged flip-up antenna that is capable of withstanding a drop
onto vinyl from 30 inches (per PCMCIA spec) while in any extended position without
damage (while out of slot). The antenna, when not in use, will fold down or rotate. The
RF output of the Aircard 555 will have a 50 ohm coaxial connection to support remotely
mounted antennas and test connections.

The gain of the antenna will be in the range of 0 to –1.0 dBi.


3.3     Architecture

A block diagram of the radio section is given below in Figure 2. The Aircard 555
wireless modem consists of two main sections, i.e. the Control Logic Circuits and the
Radio Transceiver Circuits. Qualcomm’s MSM5105 in the logic section controls all
functions in the transceiver. It is responsible for programming the synthesizer, RF power
selection, enabling and disabling the transmitter and receiver sections, and performing
electronically tuned adjustment.

 The transceiver uses a single synthesizer for both the transmitter and receiver. The
operation of the synthesizer is described in section 2.4, Frequency Generation Unit. The
synthesizer uses high-side injection for both the AMPS and PCS bands. The synthesizer
produces a frequency that is 183.6 MHz above our desired RX frequency (RX first LO)
and 263.6 MHz above our desired TX frequency for PCS (228.6 MHz for AMPS). The
transmitter and receiver are described in more detail in the appropriate sections.




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                                                 SIERRA WIRELESS INC.

  Document #:              2110622                                                 Revision:                               C                                     Page 10 of 14

Figure 2. Radio Block Diagram
                                                                                                                                                                                                         RXQD3
                                       1960 MHz SAW                                     CMY-210                                                                                                          RXQD2
                         LNA                                LNA
                                                                                                                                                                                                         RXQD1
                                                                                                                                                                                                         RXQD0
                                                                                       RF         IF
                                                                                            LO
                                                                                                                                                                                                         RXID3
                                                                                                                                                                                                         RXID2
                                                                                                                                                        183.6 MHz XTAL Filter                             RXID1
                                        882 MHz SAW
                                                                                                                                 IF Switch                                                                RXID0
                                                                                                                                                                                          IFR
                                                                                                                                                                                                        IOFFSET
                                                                                                                                                                                                        QOFFSET
                                                                                                                                                                                                         CHIPX8
                                                                                                                                                                                                          SBCK
                                                                                                                                                                                                          SBST
                                                                                                                                                                         TXCO                             SBDT
                                                                                                                                                                                                          SLEEP
                                                                    RF        IF
                                                                         LO
                                                                                                                                             IF LO Buffer
                  RX


    PCS


                               CMH82                                                                                                                                                                   SY_SENB
                                                                                                                                               IF                                                      SY_SDATA
     1900MHz




                  TX

                                                                                                                                                                                                       SY_SCLK
                                                                                                                                                                                                       AUX_OUT
               Coupler                                LNA_RANGE                                                         6dB Splitter          RF       Synthesizer


                                                                                                                                                                     TCXO
                                                                                                       RX LO Buffer                                                                                    TRK_LO_ADJ
     900MHz




                                                                                                                                               SI4133-X1
                                                                                                                                                                                       19.2 MHz TCXO
                  RX


                                                                                                                                                                                       TCXO Buffer


     CELL
                  TX
                                                                                                                                                                                                        BUF_TCXO



               Coupler         Power Detector           PWRDBK


                                                                   PA3.3V                                                                                                                                TX_I_P
                                                                                                                                             TX LO Buffer
                                                                                   PA_BIASCELL                                                                                                           TX_I_N
                                                                                                                                                                                                         TX_Q_P
                                                                                                                                                                                                         TX_Q_N


                                                         CELL PA                                                                                                                CELL
                                                                                                                  837 MHz SAW                                                             RFT
                                                                                                                                                                                                        DAC_IREF
                                                                   PA3.3V
                                                                                   PA_BIASPCS                                                                                                            SBCK
                                                                                                                                                                                                         SBDT
                                                                                                                                                                                                         SBST
                                                                                                                                                                                PCS

                                                         PCS PA                                                                                                                                        TX_AGC_ADJ
                                                                                    PA_MODE
                                                                                                                  1880 MHz SAW



                                                                                                                                                                                                        PA_ON_PCS
                                                                                                                                                                                                        PA_ON_CELL




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      Document #:      2110622               Revision:      C            Page 11 of 14


3.4     Frequency Generation Unit

The frequency generation unit (FGU) generates the local oscillator signals for the
receiver and the transmitter. It consists of a 3 phased locked loops that produces a
synthesized signal in the range of 1052.61 to 1077.61 MHz for AMPS, 2113.6 to 2173.6
MHz for PCS, and a dedicated IF LO of 367.2 MHz (2xIF) all contained within Silicon
Lab’s Si4133-X1 synthesizer. The desired frequency is programmed by the MSM via the
synthesizer control lines (SY_SENDB, SY_SDATA, SY_SCLK).

This LO signal is routed to the transmitter where it is downconverted by mixing with a
AMPS or PCS TX IF (283.6 and 228.6 MHz respectively) modulated signal to produce
our transmit carrier frequency. It is also routed to the receiver mixer where it
downconverts receive signals into the first IF of 183.6 MHz. The FGU also supplies an
IF frequency of 367.2 MHz to the IFR3000 subsystem where it is frequency divided by
two providing our second LO.

3.4.1    19.2 MHz Reference Oscillator

The Reference Oscillator produces a 19.2 MHz output sine wave signal. It has digital
temperature compensation that provides frequency stability of +/- 2.5 ppm over the
temperature range of -30 deg. C. to +80 deg. C. Total frequency stability over
temperature, voltage and load variation is +/ 0.3 ppm. The reference oscillator feeds the
SI4133-X1 synthesizer chip, MSM5105, RFT3100 and IFR3000.

3.4.2    LO Buffer Amplifiers

The output of the synthesizer (RF section) is split via a 6dB resistive splitter and fed into
two LO buffers (RX and TX). These signals are amplified by the buffers to increase its
output level providing enough LO drive to the cellular and PCS mixers. The IF LO
buffer’s output is fed to the IFR3000.

3.5     Transmitter

The transmitter produces an output frequency in the range of 824 to 849 MHz AMPS and
1850 to 1910 MHz PCS, with channel assignments as per the AMPS and PCS frequency
allocation specifications. The transmit chain consists of the RFT3100, cellular and PCS
saw filters, power amplifiers, power detectors, duplexers and a diplex filter. The majority
of the transmit duties are performed by Qualcomm’s RFT3100 O-QPSK IQ modulator
and PA driver chip. This chip consists of 2 differential IQ modulators, onboard IF
synthesizer, an upconverter, cellular and PCS PA drivers, and integrated automatic level
control circuit. The output of the FGU is mixed with the output of the modulator to
produce our desired transmit carrier in the desired band of operation. It is further


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                              SIERRA WIRELESS INC.

      Document #:     2110622               Revision:     C           Page 12 of 14

processed by filtering and amplification before being applied to the duplexer, diplexer
and antenna.


3.5.1    Power Amplifier

The PA amplifies the transmit signal to produce 200mW of RF power before being
applied to the duplexer. The PA’s gain can be switched from low power mode to high
power mode by utilizing the PA_MODE switch, large signal gain is increased by 6 dB.



3.5.2    Automatic level control

A high Z resistive power coupler is used to tap the output of the PA which is then fed
Schottky diode for power detection. The result is fed to one of the MSM’s ADC in which
the MSM uses accordingly to maintain our desired output.

3.5.3    Duplexer and Diplexer

The RF output of the PA is fed to the duplexer, which combines the transmitter and
receiver sections to use one antenna port. The duplexer also provides additional bandpass
filtering for the transmitter and receiver. To separate the AMPS and PCS bands a
diplexer is used before the antenna.


3.6     Receiver

The receiver is a single conversion super heterodyne type, with an IF of 183.6 MHz.
Receive signals coupled into the antenna passes through the diplexer and fed to the
desired bands duplexer before being fed to their respective RX front ends. For PCS the
output of the duplexer is fed to the first LNA it is then filtered by SAW bandpass filter
and then fed to the second LNA. From this point the output of the second LNA is fed to
a downconverter. The receive signal is downconverted to an IF of 183.6 MHz before
going the IF switch. For AMPS, the receive chain is very similar to that of the PCS
chain, the LNA stages and mixer stage are handled by a single chip (CMH82) rather than
discretely.

The local oscillator for this both mixers are provided by the FGU. The downconverted
signal is fed to a IF switch. This is where the AMPS and PCS receive chains common
point in the circuit. The switched signal is then bandpass filtered by a 183.6 MHz SAW
filter and then fed into the IFR3000. This IC first mixes our 183.6 MHz IF signal with a
IF LO of 183.6 MHz (generated by dividing 367.2 MHz FGU IF signal) giving us


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                               SIERRA WIRELESS INC.

      Document #:     2110622               Revision:      C           Page 13 of 14

baseband data. This signal further undergoes a series of amplifiers, limiters and serial to
parallel shift registers before being applied to MSM5105.


3.7     Baseband Audio Processing – Transmitter and Receiver

Baseband data signals to the radio are buffered, amplified and level shifted before being
applied to the transmit modulator.
Transversely, a demodulated receive signal is fed to the MSM5105 processor for
decoding.


3.8     Tuning Functions

All tuning functions in the transceiver are performed electronically. The tuning voltages
are controlled by the MSM5105 with its onboard digital-to-analog converters. The
radio’s tuning functions are described below.

3.8.1    TRK_LO_ADJ

Centering of the synthesizer reference oscillator is achieved by adjusting its DC bias (via
the TRK_LO_ADJ) to the crystal.

3.8.2    PA_ON_PCS, PA_ON_CELL

Used to switch the internal PA drivers of the RFT3100 to desired band of operation.

3.8.3    TX_AGC_ADJ

TX_AGC_ADJ controls the RF power at the output of RFT3100 device.


3.8.4    I_OFFSET, Q_OFFSET

Used to adjust the balance between the I and Q lines of the IFR3000 to give us
orthoganality.


3.8.5    SY_SENDB, SY_SDATA, SY_SCLK

Control lines for the Si4133-X1 synthesizer, used to program the three synthesizers to
operate within their desired frequency range.



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                              SIERRA WIRELESS INC.

      Document #:      2110622              Revision:     C           Page 14 of 14


3.8.6    SBCK, SBST, SBDT

This is the serial bus interface (SBI) control lines used to program the IFR3000 and RFT
3100.


3.9     Power Supply

The Aircard 555 radio draws its power from the host computer through the PCMCIA
interface.

PC_VIN, +5.0Vdc is filtered directly out of the PCMCIA connector and then used to
supply power to the transmitter and receiver. VBAT is further regulated down to
+3.0Vdc using three separate integrated circuit regulators to provide RX_POW,
TCXO_POW, TX_POW PA_BIAS and PA_3.3V, which in turn powers the receiver,
FGU, and part of the transmitter respectively. Each regulator has its own individual
control pin so it can be turned on and off independently.




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Document Created: 2004-07-06 15:36:15
Document Modified: 2004-07-06 15:36:15

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