Circuit Description

FCC ID: K66VXA-150

Operational Description

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FCCID_171509

VXA-150 Circuit Description VXA-150 CIRCUIT DESCRIPTION Receive Signal Path Incoming RF from the antenna jack is passed through a low-pass filter and high- pass filter consisting of coils L1022, L1024, L1026, L1027, L1030 & L1031, capacitors C1237, C1239, C1242, C1245, C1247, C1248, C1249, C1250, C1251, C1252, C1255 & C1257 and antenna switching diodes D1037 and D1039 (both RLS135) to the receiver front end section. Signals within the frequency range of the transceiver is applied to the receiver front end which contains RF amplifier Q1058 (2SC5226) and varactor-tuned band-pass filter consisting of coils L1013, L1017, L1020, L1021, L1028 & L1029, capacitors C1198, C1204, C1205, C1212, C1216, C1217, C1222, C1228, C1232, C1243 & C1253, and diodes D1032, D1034, D1036 & D1042 (all HVC350), then applied to the 1st mixer Q1056 (2SC5226). Buffered output from the VCO is amplified by Q1029 (2SC5226) to provide a pure 1st local signal between 143.4 and 172.4 MHz for injection to the 1st mixer. The 35.4 MHz 1st mixer product then passes through monolithic crystal filter XF1001 (35S15A, 7.5 kHz BW) which strips away all but the desired signal, which is then amplified by mixer post-amp Q1050 (2SC4215Y). The amplified 1st IF signal is applied to the AM/FM IF subsystem IC Q1049 (TK10931V), which contains the 2nd mixer, limiter amplifier, and AM/FM detector. A 2nd local signal is generated by PLL reference/2nd local oscillator Q1045 (2SC4116GR) from the 17.475 MHz crystal X1002. The 17.47 MHz signal is doubled by Q1048 (2SC4116GR) to produce the 450 kHz 2nd IF when mixed with the 1st IF signal within Q1049. The 2nd IF then passes through the ceramic filter CF1001 (ALFYM450F=K) to strip away unwanted mixer products. In the FM mode, a 2nd IF signal from the ceramic filter CF1001 applied to the limiter amplifier section of Q1049, which removes amplitude variations in the 450 kHz IF before detection of the speech by the ceramic discriminator CD 1001 (CDBM450C24T). Detected audio from Q1049 is passed through the de-emphasis, consisting of the resistors R1089, R1095, R1100 & R1149, capacitors C1104, C1105, 1 Vertex Standard Co., Ltd.

VXA-150 Circuit Description C1107 & C1151, and Q1028 (NJM2904V). In the AM mode, detected audio from Q1049 is passed through the audio amplifier Q1028 and ANL circuit, then applied to the AF amplifier Q1028. When ANL is on, the ANL MUTE gate Q1027 (UMG2) goes high, the low-pass filter/limiter consisting of capacitor C1124, resistors R1105, R1111, R1112, R1115 & R1119 and diode D1023 (BAS316) is activate, thus reducing the noises when impulse noise received. The processed audio signal from Q1028 passes through the audio mute gate Q1008 (DTC143ZUA) and the volume control to the audio power amplifier Q1009 (TDA72330), providing up to 0.4 Watts to the headphone jack or 8 Ω loudspeaker. A portion of the AF signal from the AM/FM IF subsystem Q1049 converted into DC voltage within the IC, and then passes through the AGC amplifier Q1054 (2SA1602A) and Q1055 (UMW1) to the inversion amplifiers Q1051 and Q1057 (both 2SC5226). These amplifier reduce the amplifier gain of the IF amplifier Q1050 and the RF amplifier Q1058 while receiving a strong signal. Squelch Control When a signal is received, a DC squelch control voltage appears at pin 15 of AM/FM IF subsystem Q1049 according to the receiving signal strength. This DC is applied to pin 2 of microprocessor Q1014. The DC squelch control voltage is compared with the SQL threshold level by the microprocessor Q1014. If the DC squelch control voltage is higher, pin 49 of Q1014 goes low. This signal disable the AF MUTE gate Q1008 (DTC143ZUA), thus activating the AF audio. Also, the microprocessor stops scanning, if active, and allows audio to pass through the AF MUTE gate Q1008. Transmit Signal Path Speech input from the microphone is passed through the microphone sensitivity potentiometer VR1001 and microphone amplifier Q1005-3 (NJM2902V), then applied 2 Vertex Standard Co., Ltd.

VXA-150 Circuit Description to the ALC amplifier Q1007 (AN6123MS). The amplified speech signal is passed through the high-pass filter Q1005-1 (NJM2902V) and low-pass filter Q1005-2 (NJM2904V), then applied to the power amplifier Q1052 (2SK2974) which AM modulate the Tx frequency with speech signal. When using the optional headset, the SIDETONE signal from Q1011 (UMG2) becomes “HIGH”, turning Q1012 (2SC4116GR) on, therefore a portion of the speech signal applied to the AF power amplifier Q1009 as a monitor signal. The carrier signal from the VCO Q1023 (2SC5226) passes through the buffer amplifier Q1029 (2SC5226) and TX/RX switch D1031 (MC2848), then amplified by Q1043 (2SC3356) and Q1047 (2SK2973), then applied to the power amplifier Q1052 which increases the signal level up to 5 watts output power. The transmit signal then passes through the antenna switch D1037 (RLS135), and is low-pass filtered to suppress away harmonic spurious radiation before delivery to the antenna. Automatic Transmit Power Control RF power output from the final amplifier is sampled by C1241/C1244 and is rectified by D1040 (HSM88WA). The resulting DC voltage passes through the Automatic Power Controller Q1005 (NJM2902V) to the APC attenuator D1015 (RN739F) and final amplifier Q1052, so as to control the power output. Transmit Inhibit When the transmit PLL is unlocked, pin 7 of PLL chip Q1032 (MB15A01PFV1) goes to a logic low. The resulting DC “unlock” control voltage is switches off TX inhibit switches Q1035 (2SA1602A), Q1037 (UMW1) and Q1041 (DTA143EU) to disable the supply voltage to transmitter RF amplifiers Q1043, disabling the transmitter. Spurious Suppression Generation of spurious products by the transmitter is minimized by the fundamental carrier frequency being equal to the final transmitting frequency. 3 Vertex Standard Co., Ltd.

VXA-150 Circuit Description Additional harmonic suppression is provided by a low-pass filter consisting of L1024, L1026 & L1030 and C1242, C1245, C1247, C1249, C1252 & C1257, resulting in more than 60 dB of harmonic suppression prior to delivery of the RF signal to the antenna. PLL Frequency Synthesizer PLL circuitry consists of VCO Q1023 (2SC5226), VCO buffer Q1029 & Q1036 (both 2SC5226), and PLL subsystem IC Q1032 (MB15A01PFV1), which contains a reference divider, serial-to-parallel data latch, programmable divider, phase comparator and charge pump. Stability is maintained by a regulated 3.5 V supply via Q1030 (S-81235SGUP-DQI) which feeds the PLL reference oscillator Q1045 (2SC4116GR), as well as capacitors associated with the 17.475 MHz frequency reference crystal X1002. In the receive mode, VCO Q1023 oscillates between 143.4 and 172.4 MHz. The VCO output is buffered by Q1029 and Q1036, and applied to the prescaler section of Q1032. There the VCO signal is divided by 64 or 65, according to a control signal from the data latch section of Q1032, before being applied to the programmable divider section of Q1032. The data latch section of Q1032 also receives serial dividing data from the microprocessor Q1014 (M38254M6), which causes the pre-divided VCO signal to be further divided in the programmable divider section, depending upon the desired receive frequency, so as to produce a 5 kHz derivative of the current VCO frequency. Meanwhile, the reference divider section of Q1032 divides the 17.475 MHz crystal reference from the reference oscillator Q1045 by 3495 to produce the 5 kHz loop reference. The 5 kHz signal from the programmable divider (derived from the VCO) and that derived from the reference oscillator are applied to the phase detector section of Q1032, which produces a pulsed output with pulse duration depending on the phase difference between the input signals. This pulse train is filtered to DC and returned to the varactor D1015 (HVC350B). Changes in the level of the DC voltage applied to the varactors affect the reactance in the tank circuit of the VCO, changing the oscillating frequency of the VCO according to the phase difference between the signals derived from the VCO and the crystal reference oscillator. The VCO is thus phase-locked to the crystal reference 4 Vertex Standard Co., Ltd.

VXA-150 Circuit Description oscillator. The output of the VCO Q1023 is buffered by Q1029 before application to the 1st mixer, as described previously. For transmission, the VCO Q1023 oscillates between 118 and 137 MHz. The remainder of the PLL circuitry is shared with the receiver. However, the dividing data from the microprocessor is such that the VCO frequency is at the actual transmit frequency (rather than offset for IFs, as in the receiving case). Receive and transmit buses select which VCO is made active by Q1021 (RT1N241M). FET Q1042 (2SK880GR) buffers the VCV line for application to the tracking band- pass filters in the receiver front end. When the power saving feature is active, the microprocessor periodically signals to the PLL IC Q1032 to conserve power, and to shorten lock-up time. Push-To-Talk Transmit Activation The PTT switch on the microphone is fed through the PTT controller, Q1002 (UMZ2N), to pin 41 of microprocessor Q1014, so that when the PTT switch is closed, pin 18 of Q1014 goes high. This signals the microprocessor to activate the TX/RX controller Q1017 (UMG2N), which cut off the receiver by disabling the 5 V supply bus at Q1020 (DTA143EU) which feeds the front-end, FM IF subsystem IC Q1049, and receiver VCO circuitry. At the same time, Q1037 (UMW1) and Q1041 (DTA143EU) activates the transmit 5 V supply line to enable the transmitter. 5 Vertex Standard Co., Ltd.


Document Created: 2001-08-16 18:00:48
Document Modified: 2001-08-16 18:00:48
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