Circuit Description

FCC ID: K66VX-4000UE

Operational Description

Download: PDF
FCCID_130475

                                                             headphone jack or 4-ohm loudspeaker.
Circuit Description
                                                             PLL synthesizer
                                                               The 1st LO maintains stability from the PLL synthesizer
Reception and transmission are switched by “RX” and ”
                                                             by using a 14.500 MHz reference signal from crystal
TX” lines from the microprocessor unit (MPU). The
                                                             X1001. PLL synthesizer IC Q1024 (SA7025DK) consists
receiver uses double-conversion superheterodyne
                                                             of a prescaler, reference counter, swallow counter,
circuitry, with a 43.95MHz 1st IF and 450 kHz 2nd IF. The
                                                             programmable counter, a serial data input port to set
1st LO, produced by a PLL synthesizer, yields the
                                                             these counters based on the external data, a phase
43.95MHz 1st IF.
                                                             comparator, and charge pump. The PLL-IC divides the
 The 2nd LO uses a 43.5 MHz (43.95 MHz-450 kHz)
                                                             14.500 MHz reference signal by 725 using the reference
signal generated by a crystal oscillator. The 2nd mixer
                                                             counter (20.0 kHz comparison frequency). The phase
and other circuits use a custom IC to convert and amplify
                                                             detector comparison frequency to be eight times the
the 2nd IF, and detect FM to obtain demodulated signals.
                                                             channel spacing (2.5kHz). The VCO output is divided by
During transmit, the PLL synthesizer oscillates at the
                                                             the prescaler, swallow counter and programmable
desired frequency directly, for amplification to obtain RF
                                                             counter. These two signals are compared by the phase
power output. During transmit, voice modulation and
                                                             comparator and input to the charge pump. A voltage
CTCSS (or DCS) modulation are applied to this
                                                             proportional to their phase difference is delivered to the
synthesizer. Transceiver functions, such as TX/RX
                                                             low-pass filter circuit, then fed back to the VCO as a
control, PLL synthesizer settings, and channel
                                                             voltage with phase error, controlling and stabilizing the
programming, are controlled using the MPU.
                                                             oscillating frequency. This synthesizer also operates as a
                                                             modulator during transmit.
                                                               The RX-VCO is comprised of Q1015 (2SK520) and
VHF                                                          D1017, D1018, D1035, D1036 (HVU356x4), and
                                                             oscillates between 177.950MHz and 217.950MHz
Receiver                                                     according to the programmed receiving frequency. And
Incoming RF signals from the antenna connector are           the TX-VCO is comprised of Q1014 (2SC5107) and
delivered to the MAIN Unit, and pass through a low-pass      D1015, D1016, D1019 (1SV276x3), and oscillates
filter (LPF) antenna switching network consisting of coils   between 134.000MHz and 174.000MHz according to the
L1001, L1002, L1003 and L1006, capacitors                    programmed transmit frequency. The VCO output
C1001,C1006, C1009, C1013, and C1023, and antenna            passes through buffer amplifier Q1018 (2SC5107), and a
switching diodes D1006,D1007 and D1008 for delivery to       portion is fed to the buffer amplifier Q1019 (2SC5107) of
the receiver front end.                                      the PLL IC, and at the same time amplified by Q1021
Signals within the frequency range of the transceiver are    (2SC5107) to obtain stable output. The VCO DC supply
then passed through a varactor-tuned bandpass filter         is regulated by Q1008 (2SC4154E). Synthesizer output is
consisting of L1008, L1009 / L1024, L1025 before RF          fed to the 1st mixer by diode switch D1024 (1SS321)
amplification by Q1012 (3SK228).                             during receive, and to drive amplifier Q1020/Q1022
The amplified RF is then band-pass filtered again by         (2SC5415Ex2) for transmit. The reference oscillator
varactor-tuned resonators L1018, L1019 / L1038, L1039        feeds the PLL synthesizer, and is composed of crystal
to ensure pure in-band input to 1st mixer                    X1001 (14.500 MHz), the temperature compensation
Q1025(2SK228).                                               circuit which includes D1033 (MC2850) and thermostats
  Buffered output from the VCO Unit is amplified by          TH1003 and TH1002, and transmit (DCS) modulation
Q1021 (2SC5107) and low-pass filtered by L1042 /             circuit D1029 (1SV2309).
L1046 and C1132 / C1139 / C1142, to provide a pure 1st
local signal between 112.3 and 152.3 MHz to the 1st          Transmitter
mixer.                                                         Voice audio from the microphone is delivered via the
The 43.95MHz 1st mixer product then passes through           Mic (Jack) Unit to the MAIN Unit, after passing through
dual monolithic crystal filters XF1001 and XF1002 (7.5       amplifier Q3039/Q2108 (NJM2902V), pre-emphasis,
kHz BW), and is amplified by Q1029 (2SC4215Y) and            limiter (IDC instantaneous deviation control) ,and LPF
delivered to the input of the FM IF subsystem IC Q1026       Q2001 (NJM2902V), is adjusted for optimum deviation
(TA31136FN).                                                 level and delivered to the next stage.
This IC contains the 2nd mixer, 2nd local oscillator,          Voice input from the microphone and CTCSS are FM-
limiter amplifier, FM detector, noise amplifier, and         modulated to the VCO of the synthesizer, while DCS
squelch gates.                                               audio is modulated by the reference frequency oscillator
The 2nd LO in the IF-IC is produced from crystal X1001       of the synthesizer.
(14.500MHz), and the 1st IF is converted to 450kHz by          Synthesizer output, after passing through diode switch
the 2nd mixer and stripped of unwanted components by         D1024 (1SS321), is amplified by driver Q1020 / Q1022
ceramic filter CF1001 or CF1002. After passing through a     (2SC5415Ex2) and power module Q1013 (M67746) to
limiter amplifier, the signal is demodulated by the FM       obtain full RF output. The RF energy then passes through
detector.                                                    antenna switch D1007 / D1008 and a low-pass filter
Demodulated receive audio from the IF-IC is amplified by     circuit and finally to the antenna connector.
Q1031 (2SA1602A) / Q2014 (CXA1846N). After volume              RF output power from the final amplifier is sampled by
adjustment by the AF power amplifier Q2029                   CM coupler and is rectified by D1011, D1014
(TDA7240AV), the audio signal is passed to the optional


(HSM88ASx2). The resulting DC is fed through                 kHz BW), and is amplified by Q1029 (2SC4215Y) and
Automatic Power Controller Q1007 (NJM2904V), Q1001           delivered to the input of the FM IF subsystem IC Q1026
(2SC4154E), Q1002 (2SB1143S) to transmitter RF               (TA31136FN).
amplifier and thus the power output.                           This IC contains the 2nd mixer, 2nd local oscillator,
Generation of spurious products by the transmitter is        limiter amplifier, FM detector, noise amplifier, and
minimized by the fundamental carrier frequency being         squelch gates.
equal to the final transmitting frequency, modulated           The 2nd LO in the IF-IC is produced from crystal X1001
directly in the transmit VCO. Additional harmonic            (14.500MHz), and the 1st IF is converted to 450kHz by
suppression is provided by a low-pass filter consisting of   the 2nd mixer and stripped of unwanted components by
L1002, L1003, L1007, L1012 and C1006, C1009, C1013,          ceramic filter CF1001 or CF1002. After passing through a
C1023, C1033, C1037 and C1046, resulting in more than        limiter amplifier, the signal is demodulated by the FM
60dB of harmonic suppression prior to delivery to the RF     detector.
energy to the antenna.                                         Demodulated receive audio from the IF-IC is amplified
                                                             by Q2014 (CXA1846N). After volume adjustment by the
DCS Demodulator                                              AF power amplifier Q2029 (TDA7240AV), the audio
DCS signals are demodulated on the MAIN-UNIT, and            signal is passed to the optional headphone jack or 4-ohm
are applied to low-pass filter Q2110 (NJM2902V), as well     loudspeaker.
as the limiter comparator Q2110.
                                                             PLL synthesizer
CTCSS encoder/decoder                                          The 1st LO maintains stability from the PLL synthesizer
The CTCSS code is generation and encoding by MPU IC          by using a 14.500 MHz reference signal from crystal
Q2019 (MB90F583B).                                           X1001. PLL synthesizer IC Q1024 (SA7025DK) consists
Demodulation and detection of the CTCSS tones are            of a prescaler, reference counter, swallow counter,
carried out by IC Q2013 (MX165C).                            programmable counter, a serial data input port to set
                                                             these counters based on the external data , a phase
MPU                                                          comparator, and charge pump. The PLL-IC divides the
Operation is controlled by 16-bit MPU IC Q2019               14.500 MHz reference signal by 725 using the reference
(MB90F583B). The system clock uses a 16.000 MHz              counter (20.0 kHz comparison frequency). The phase
crystal for a time base. IC Q2027 (S-80735SN) resets the     detector comparison frequency to be eight times the
MPU when the power is on, and monitors the voltage of        channel spacing (2.5kHz). The VCO output is divided by
the regulated 5V power supply line.                          the prescaler, swallow counter and programmable
                                                             counter. These two signals are compared by the phase
EEPROM                                                       comparator and input to the charge pump. A voltage
 The EEPROM retains TX and RX data for all memory            proportional to their phase difference is delivered to the
channels and CTCSS data, DCS data, prescaler dividing,       low-pass filter circuit, then fed back to the VCO as a
and REF oscillator data (internal/external).                 voltage with phase error, controlling and stabilizing the
                                                             oscillating frequency. This synthesizer also operates as a
                                                             modulator during transmit.
                                                               The RX-VCO is comprised of Q1015 (2SK508) and
                                                             D1017, D1018 (1SV276x4), and oscillates between
UHF                                                          356.050MHz and 468.050MHz according to the
                                                             programmed receiving frequency. And the TX-VCO is
Receiver                                                     comprised of Q1014 (2SC4226) and D1015, D1016,
Incoming RF signals from the antenna connector are           D1019 (1SV276x2, 1SV230), and oscillates between
delivered to the MAIN Unit, and pass through a low-pass      400.000MHz and 512.000MHz according to the
filter (LPF) antenna switching network consisting of coils   programmed transmit frequency. The VCO output
L1001, L1002, L1003,L1004 and L1005, capacitors              passes through buffer amplifier Q1018 (2SC5107), and a
C1004, C1008,C1009, C1011, and C1014, and antenna            portion is fed to the buffer amplifier Q1019 (2SC5107) of
switching diodes D1006,D1007 and D1008 for delivery to       the PLL IC, and at the same time amplified by Q1021
the receiver front end.                                      (2SC5107) to obtain stable output. The VCO DC supply
Signals within the frequency range of the transceiver are    is regulated by Q1008 (2SC4154E). Synthesizer output is
then passed through a varactor-tuned bandpass filter         fed to the 1st mixer by diode switch D1024(1SS321)
consisting of L1009, L10014 before RF amplification by       during receive, and to drive amplifier Q1020 (2SC5107) /
Q1012 (2SK4227).                                             Q1022 (2SC5415E) / Q1031 (2SC2954) for transmit. The
The amplified RF is then band-pass filtered again by         reference oscillator feeds the PLL synthesizer, and is
varactor-tuned resonators L1022, L1026 to ensure pure        composed of crystal X1001 (14.500 MHz), the
in-band input to 1st mixer Q1025 (2SK228).                   temperature compensation circuit which includes D1033
Buffered output from the VCO Unit is amplified by Q1021      (MC2850) and thermostats TH1003 and TH1002, and
(2SC5107) and low-pass filtered by L1030 / L1031 and         transmit (DCS) modulation circuit D1029 (1SV230).
C1178 / C1180 / C1182, to provide a pure 1st local signal
between 112.3 and 152.3 MHz to the 1st mixer.                Transmitter
The 43.95MHz 1st mixer product then passes through            Voice audio from the microphone is delivered via the
dual monolithic crystal filters XF1001 and XF1002 (7.5       Mic (Jack) Unit to the MAIN Unit, after passing through


amplifier Q3039/Q2108 (NJM2902V), pre-emphasis,
limiter (IDC instantaneous deviation control) ,and LPF
Q2001 (NJM2902V), is adjusted for optimum deviation
level and delivered to the next stage.
Voice input from the microphone and CTCSS are FM-
modulated to the VCO of the synthesizer, while DCS
audio is modulated by the reference frequency oscillator
of the synthesizer.
  Synthesizer output, after passing through diode switch
D1024 (1SS321), is amplified by driver Q1020
(2SC5107) / Q1022 (2SC5415E) / Q1031 (2SC2954) and
power module Q1013 (M68759) to obtain full RF output.
The RF energy then passes through antenna switch
D1007 / D1008 and a low-pass filter circuit and finally to
the antenna connector.
  RF output power from the final amplifier is sampled by
CM         coupler      and        is    rectified     by
D1011,D1014(HSM88ASx2). The resulting DC is fed
through Automatic Power Controller Q1007 (NJM2904V),
Q1001 (2SC4154E), Q1002 (2SB1143S) to transmitter
RF amplifier and thus the power output.
  Generation of spurious products by the transmitter is
minimized by the fundamental carrier frequency being
equal to the final transmitting frequency, modulated
directly in the transmit VCO. Additional harmonic
suppression is provided by a low-pass filter consisting of
L1001, L1003, L1004 and C1004, C1008, C1009, C1011
and C1014, resulting in more than 60dB of harmonic
suppression prior to delivery to the RF energy to the
antenna.

DCS Demodulator
 DCS signals are demodulated on the MAIN-UNIT, and
are applied to low-pass filter Q2110 (NJM2902V), as well
as the limiter comparator Q2110.

CTCSS encoder/decoder
 The CTCSS code is generation and encoding by MPU
IC Q2019 (MB90F583B).
Demodulation and detection of the CTCSS tones are
carried out by IC Q2013 (MX165C).

MPU
 Operation is controlled by 16-bit MPU IC Q2019
(MB90F583B). The system clock uses a 16.000 MHz
crystal for a time base. IC Q2027 (S-80735SN) resets the
MPU when the power is on, and monitors the voltage of
the regulated 5V power supply line.

EEPROM
The EEPROM retains TX and RX data for all memory
channels and CTCSS data, DCS data, prescaler dividing,
and REF oscillator data (internal/external).



Document Created: 2000-07-14 01:21:33
Document Modified: 2000-07-14 01:21:33

© 2025 FCC.report
This site is not affiliated with or endorsed by the FCC