CIRCUIT DESCRIPTION

FCC ID: K6610614640

Operational Description

Download: PDF
FCCID_813475

FCC ID: K6610614640 IC ID: 511B-10614640 Circuit Description VX-2100/VX-2200 (UHF) Circuit Description 1. Circuit Configuration by Frequency The receiver is a double-conversion superheterodyne with a first intermediate frequency (IF) of 67.65 MHz and a second IF of 450 kHz. Incoming signal from the antenna is mixed with the local signal from the VCO/PLL to produce the first IF of 67.65MHz. This is then mixed with the 67.2 MHz second local oscillator output to produce the 450 kHz second IF. This is detected to give the demodulated signal. The transmit signal frequencies generated by the PLL VCO and modulated by the signal from the microphone. It is then amplified and sent to the antenna. 2. Receiver System 2-1. Front-end RF amplifier Incoming RF signal from the antenna is delivered to the RF Unit and passes through Low- pass filer, and removed undesired frequencies by varactor diode. Tuned band-pass filer consisting of diodes D1004 and D1005, and Coils L1006 and L1009, capacitors C1013, C1016, C1033, C1041 and C1044. The passed signal is amplified in Q1007 and moreover cuts an image frequency with the band path filter consisting of Coils L1011, L1013, L1014 and L1015, and capacitors C1039, C1103, C1111, C1112, C1116, C1122, C1123, C1127, C1128, C1130, C1134 and C1141 comes into the 1st mixer. 2-2. First Mixer The 1st mixer consists of the Q1025. Buffered output from the VCO is amplified by Q1023 to provide a pure first local signal between 332.35 and 402.35 MHz for injection to the first mixer. The output IF signal is enters from the mixer to the crystal filter. The IF signal then passes through monolithic crystal filters XF1001 (±5.5 kHz BW) to strip away all but the desired signal. 2-3. IF Amplifier The first IF signal is amplified by Q1033. The amplified first IF signal is applied to FM IF subsystem IC Q1036 which contains the second mixer second local oscillator limiter amplifier noise amplifier and S-meter amplifier. The signal from reference oscillator X1002 becomes 3 times of frequencies in Q1033, it is mixed with the IF signal and becomes 450 kHz. The second IF then passes through the ceramic filter CF1001 (for wide channels) CF1002 (for narrow channels) to strip away unwanted mixer products which removes 1/4 Vertex Standard Co., Ltd.

FCC ID: K6610614640 IC ID: 511B-10614640 Circuit Description amplitude variations in the 450 kHz IF before detection of the speech by the ceramic discriminator CD1001. 2-4. Audio amplifier Detected signal from Q1036 is inputted to Q1042 and is output through the band path filter inside Q1042. When the optional unit is installed the Q1044 is turned “ OFF” and the AF signal from Q1042 goes the optional unit. When the optional unit is not installed, Q1042 is turned “ ON” and the signal goes through Q1004. The signal then goes through AF mute switch Q1044 and de-emphasis part Q1042 amplified with AF power amplifier Q1003 after passing AF volume Q1014. The output of Q1003 drives a speaker (either internal or external speaker). 2-5. Squelch Circuit There are 13 levels of squelch setting from 0 to 12. The level 0 means open the squelch. The level 1 means the threshold setting level and level 11 means tight squelch. From 2 to 10 is established in the middle of threshold and tight. The bigger figure is nearer the tight setting. The level 12 becomes setting of carrier squelch. 2-5-1. Noise Squelch Noise squelch circuit is composed of the band path filter of Q1036 and noise amplifier Q1047 and noise detector D1047, D1048. When no carrier received, the noise ingredient which goes out of the demodulator Q1036 is amplified in Q1047 through the band path filter Q1036 is detected to DC voltage with D1047, D1048 and is inputted to 15 pin (the A/D port) of the Q1065. When a carrier is received the DC voltage becomes “ LOW” because the noise is compressed. When the detected voltage to CPU is “ HIGH,” the CPU stops AF output with Q1044 “ OFF” by making the pin 80 “ L” level. When the detection voltage is low the CPU makes Q1068 “ ON” with making pin 80 “ H” and the AF signal is output. 2-5-2. Carrier Squelch The pin 14 (A/D port) of Q1065 detects RSSI voltage output from pin 12 of Q1036, and controls AF output. The RSSI output voltage changes according to the signal strength of carrier. The stronger signal makes the RSSI voltage to be higher voltage. The process of the AF signal control is same as Noise Squelch. The shipping data is adjusted 3 dB higher than squelch tight sensitivity. 2/4 Vertex Standard Co., Ltd.

FCC ID: K6610614640 IC ID: 511B-10614640 Circuit Description 3. Transmitter System 3-1. Mic Amplifier The AF signal from microphone jack J1004 (front) or J1006 (D-sub) is amplified with microphone amplifier Q1046 is amplified with 2nd microphone amplifier Q1043 after microphone selection switch Q1004, and passes microphone gain volume Q1014. The control from the CPU it passes output and it passes a pre-emphasis circuit. Q1044 becomes “ OFF” when an option unit is attached and the AF signal from Q1040 goes via the option unit. When an option unit is not attached Q1044 becomes “ ON,” the signal passes Q1044 and is input to Q1040. The signal passed limiter and splatter filer of Q1040 is adjusted by maximum deviation adjustment volume Q1014. The adjusted low frequency signal ingredient is amplified by Q1043 added modulation terminal of TCXO (X1002) the FM modulation is made by reference oscillator. The high frequency signal ingredient is amplified Q1043, and adjusted the level by volume Q1014 to make frequency balance between low frequency. After that it is made FM modulation to transmit carrier by the modulator D1023 of VCO. 3-2. Drive and Final amplifier The modulated signal from the VCO Q1031 is buffered by Q1027 and amplified by Q1015. The low-level transmit signal is then applied to the Power Module Q1009 for final amplification up to 45 watts output power. The transmit signal then passes low-pass filtered to suppress away harmonic spurious radiation before delivery to the antenna. 3-3. Automatic Transmit Power Control The output power of Power Module is detected by CM coupler, it is detected by D1008 and D1038 and is input to comparator Q1048. The comparator compares two different voltages and makes output power stable by controlling the bias voltage of Power Module. There are 3 levels of output power (Hi, Mid and Lo) it is switched by the voltage of Q1014-CH1. 3-4. PLL Frequency Synthesizer The frequency synthesizer consists of PLL IC Q1054 VCO, TCXO (X1002) and buffer amplifier. The output frequency from TCXO is 16.8 MHz and the tolerance is ±2.5 ppm (in the temperature range -30 to +60 degrees). 3-4-1. VCO While the radio is receiving, the RX oscillator Q1029 in VCO generates a programmed 3/4 Vertex Standard Co., Ltd.

FCC ID: K6610614640 IC ID: 511B-10614640 Circuit Description frequency between 332.35 and 402.35 MHz as 1st local signal. While the radio is transmitting the TX oscillator Q1031 in VCO generates a frequency between 400 and 470 MHz. The output from oscillator is amplified by buffer amplifier Q1027 and becomes output of VCO. The output from VCO is divided one is amplified by Q1024 and feed back to pin 6 of the PLL IC Q1054. The other is amplified in Q1023 and in case of the reception it is put into the mixer as the 1st local signal through D1020 in transmission it is amplified in Q1038 and more amplified in Q1015 through D1022 and it is put the input terminal of the Power Module Q1009. 3-4-2. VCV CNTL Tuning voltage (VCV) of VCO is expanding the lock range of VCO by controlling the of varactor diode at the voltage and the control voltage from PLL IC Q1054. Control voltage is added to the varactor diode after converted to D/A converter Q1029. 3-4-3. PLL The PLL IC Q1054 consists of reference divider, main divider, phase detector, charge pumps and fractional accumulator. The reference frequency from TCXO is inputted to pin 8 of PLL IC Q1054 and is divided by reference divider. This IC is decimal point dividing PLL IC Q1054 and the dividing ratio becomes 1/8 of usual PLL frequency step. Therefore, the output of reference divider is 8 times of frequencies of the channel step. For example when the channel stepping is 5 kHz, the output of reference divider becomes 40 kHz. The other hand inputted feed back signal to pin 6 of PLL IC Q1054 from VCO is divided with the dividing ratio, which becomes same frequency as the output of reference divider. These two signals are compared by phase detector, the phase difference pulse is generated. The phase difference pulse and the pulse from fractional accumulator pass through the charge pumps and LPF. It becomes the DC voltage (VCV) to control the VCO. The oscillation frequency of VCO is locked by the control of this DC voltage. The PLL serial data from CPU Q1065 is sent with three lines of SDO (pin 12), SCK (pin 11) and PSTB (pin 13). The lock condition of PLL is output from the UL (pin 14) terminal and UL becomes “ H” at the time of the lock condition and becomes “ L” at the time of the unlocked condition. The CPU Q1065 always watches over the UL condition, and when it becomes “ L” unlocked condition, the CPU Q1065 prohibits transmitting and receiving. 4/4 Vertex Standard Co., Ltd.


Document Created: 2007-06-04 12:08:38
Document Modified: 2007-06-04 12:08:38
© 2024 FCC.report
This site is not affiliated with or endorsed by the FCC