Block diagram

FCC ID: H9P2164436

Block Diagram

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FCCID_376248

The 24-64436 PCB is logically divided into two parts: a digital/analog system and a radio. Both are located on the same PCB, however are physically separate from each other. The Figures 1 and 2 below depicts a block diagram of the entire PCB system. The on-board radio (which is being type approved) is shown here as only one of the blocks. Pico Decoded Scanner Imager or 1D (SE1200HP) FFUART (SE1224, color or 2D (SE2200) Lorax) camera Main Terminal Module (MTM) OLED interface, Scanner/ Imager Main flex related - all ESD & EMI protected T3 802.11b display (future) Decoded Conn. Core 3.3V @ 3A Conn. (25) (30) Integrated Radio 1.3V Core Power RS232 External EMI Protected EMI Protected 3.6MHz & PLL Supply Driver from 3.3V power USB 5V Two Color interface, crystal TP Conn. Supply ASIC switch & detect Two antenna LCD & TP 3.6MHz Antennas (4) UART1 current limit connectors EMI Protected resonator 32/64/128 Outhouse (diversity) PXA255 XScale CPLD Mono interface, Display MByte Power CPU @ 400Mhz Keypad EL Piezo Backup LCD & TP Conn. (51) SDRAM EMI Protected Micro Panel speaker battery Reset Circuit backlight supply & charger & Address & EMI / noise 32/64 MByte Trigs. Trig<2..3> filtering Strata Flash driver driver regulator Conn. (3) Data Legend: (handle or Buffers 32.768 KHz side EMI Protected Addr./Ctrl I/O Connector Main Backup Off-board component (Level 2) oscillator 3 cell Data Buffers (main flex) Battery battery triggers) Buffers NiMH (Level 1) (100) Charger connector Connector (Level 1) LH ASIC backup 2 Option connectors (2) (numbers in (80 pins each) EMI Protected batt Logical or physical parantheses grouping of represent the number components/ of pins on the MTM connections connectors) Figure 1: High level block diagram – entire PCB

32.768 kHz JTAG Osc. MMC/SD Main Flex Connector 32.768 KHz IrDA (used for keypad comm) Cotulla USB (4) XScale CPU 3.6MHz 3.6864 MHz GPIO7 / 48MHz 48 MHz Display Connector (51) FFUART To Imaging To Communications Connector Connector TP 3.6864 LCD Signals (20) Control (9) I2C (2),GPIO (2) MHz BT UART+CTRL JTAG (5) CPLD_CLK_32K UART1+PWR+CTRL +5V (for Corona) RAW_DC 3.3V Cotulla-side option connector UART2/DEBUG +3.3V I/O Devices I/O Device Bus (80 pins) Core & PWR_SW* PLL LCD LCD Signals TRIG0* & TRIG4* CORE_EN* LEVEL 2 Power BUFFER Supplies ENABLE CONTROL SDCS0* SDRAM 32/64MB/128MB Strata Flash (J3 or K3) CS0* LOGIC SDCS1* RAW_DC To Power (x2) 32/64MB (x2) Add [10..24] Micro Control (9) Control (6) (32) (32) Add [2..25] JTAG Control RESET Data XM_DATA[0..31] ⇔Buffer (32 bit) BX_DATA[0..31] BX_DATA[0..16] ⇔Buffer (16 bit) BBX_DATA[0..16] 3.6864 MHz IC PWR_EN +3.3V Address XM_ADDR[0..25] ⇔Buffer (32 bit) BX_ADDR[0..25] BBX_ADDR[0..25] ASIC-side option connector =>Buffer (32 bit) 3.6864 MHz BUFF_3.6864 MHz (80 pins) R/W BUFF_R/W RAW_DC (BUFEN) Control Control PCMCIA SLOT B CTRL (20) BATT_FAULT* Chip Selects CS[0..5] CS0* CS0*, CS1*, (MBGNT) SDRAM ctrl (9) RESET* (TO FLASH) (2) Piezo AUDIO_INTO_MTM PWR_SW* GPIO0/ Reset Analog speaker CS4* PWRSW MUX BEEP (from ASIC) LH_IRQ Main Flex power From I/O Device Bus LH_ IRQ Chip Selects ⇔Buffer (16 bit) Sync Flash Ctrl (2) - SDCLK0 & SDCAS Connector supply & (I2C and GPIO) 48 MHz (4) CODEC_PRESENT (BUFEN) driver 3.6864 MHz D_DIR & BUF_EN To (4) DBG_CS* various 32.768 KHz Imaging BATT_EMERGENCY I/O register places, EXT_CS* EXT_CS* Connector (20) Imaging BX_ADDR[17..19] (part of Outhouse see (30) detailed CPLD) matrix SDRAM ctrl (9) Battery BX_DATA[16..23] CORE_EN Backup Backup 1D/2D/ Scanner Charger Connector 3.0V reg. Decoded (16) Interface Control RESET (2) Scanner (25) Chip Power Fault RAW_DC LH ASIC Address (0-25) Trigger Detect Connector TRIG[2..3]* Trig[0..4]* Data (0-31) 3.68MHz Reset_in CORE_EN Touch RESET* Resonator Panel (3) CRADLE_DET Logic for JTAG and POWER_FAULT* EXT_PWR_EN Reset Reset_out UART 1_ENABLE debug 3.3V Main Flex SPI (5) SPI Power Micro Regulator 3.3V (8) UART 1 Connector FUNC LED UART 2 I/O Device Bus 32.768 KHz (also input COMM LED switching) DECODE LED BE* Power SCAN LED BE* I2C_BATT Keyboard Backlight Switch* ACIN To option TRIG0*&4* JTAG (5) Matrix Keyboard PC PC Slot Slot 0 A TRIG[0..1]* board conn BATT+ BATT- Logic for (2A max) (2A max) BT_MEDIUM_FREE BATT_FAULT* BATT_FAULT Main Flex Main Flex Conn (10) (16) (50) (to option board conn) Controlled by ASIC 3A max Connector From I/O Smart (POWER_IN) Device Bus Battery CPLD_CLK_32K 2 Cell Li- 802.11b S24 Power Note: Battery is 7.2V radio (T3 CF) FET 3.3V Ion >=2200mAH Main Flex Connector Charger Debounce 3.6864 MHz (part of Power Outhouse Switch* Voltage CPLD) detector (2) Figure 2: Detailed block diagram – entire PCB

Figures 3 and 4 below depict detailed block diagrams of the on-board radio. PCMCIA Host I/F HFA3873 Radio MicroController Prism 2.5 Based Clock EEPROM SRAM Figure 3: Overall block diagram of on-board radio

Figure 4: Intersil Prism 2.5 chipset (basis for on-board radio)


Document Created: 2003-10-29 15:51:02
Document Modified: 2003-10-29 15:51:02
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