response to 13281

FCC ID: H25DSS950TX

Cover Letter(s)

Download: PDF
FCCID_95633

April 11, 2000


Mr. Joe Dichoso
Federal Communications Commission
Laboratory Division
7435 Oakland Mills Road
Columbia, MD 21046

Michael J. Murphy
75 Northeastern Blvd.
Nashua, NH 03062
(603) 668-8549 FAX (603) 880-6965

Attention:          Mr. Dichoso


                    Re:       Answers to questions from E-mail of 04/05/00
                              Correspondence Reference Number: 13281
                              FCC ID: H25DSS950TX
                              731 Confirmation Number EA96934
                              Equipment Class: DSS-Part 15 Spread Spectrum Transmitter
                              Applicant: DTC



DTC has collected additional data on H25DSS950TX in order to satisfy all six questions on the referenced E-mail.

1.   The antenna gain of the integral patch antenna on the DSS950TX is 2 dBi.

2.   Additional photos have been taken of all three boards; front and back with all shields removed. These are attached to this document as
     EXHIBIT 1.

3.   The full SAR report was uploaded separately from the Test Data package in the original filing. Mr. Errol Chang as normally requests
     this to be a separate package for Part-15 submissions.

4.   Data have been taken at 50 Second and 100 Second sweep times in order to satisfy the 67 Second sweep time request. Our equipment
     can not provide this exact sweep time. These are attached to this document as EXHIBIT 2.

5.   DTC requests confidentiality only on its schematics. Disregard the request on the processing gain data package.

6.   The processing gain measurements do apply to this device since Digital Wireless Corp (DWC) did the entire turn-key DSS core
     design, and DTC has not changed it in any way critical to processing gain. In fact, the receiver hardware portion is still purchased
     from Digital Wireless Corp. The changes to the transmitter circuit made by DTC involve signal amplification and harmonic filtering
     and antenna design; all external to the DWC exciter board design. These do not impact the emissions generated inside the occupied
     bandwidth. We have not changed the chipping rate, clock, FIR filter firmware or data rate or data filtering, all of which could impact
     the processing gain. We have not changed the exciter board layout. The second point that the FCC made was that the data provided by
     DWC was non-compliant. Utilizing the theoretical S/N ratio for coherently detected BPSK for a .0001 BER (9.6 dB) in the equation,
     the unit certainly would be non-compliant. But the actual S/N number stated for a .0001 BER for the receiver as built with differential
     BPSK detection is 12-14 dB; also from the DWC package (when queried last week, DWC engineer said to use 13 dB). Using the
     equation: Gp =S/N + Lsys + (J/S) ; Gp = 13 + 2 + (2.9) = 12.1 dB, which is compliant.


Best Regards,


Michael J. Murphy
Electronics Engineer
DTC Communications, Inc.
mmurphy@dtccom.com


EXHIBIT 1 PHOTOS

DSS EXCITER WITH VCO SHIELD REMOVED




DSS EXCITER BACK


½ W POWER AMPLIFIER – FRONT




PA BACK


POWER SUPPLY – FRONT




BACK


EXHIBIT 2 SPECTRAL PLOTS at 50S and 100S SWEEP on Marconi 2383



Document Created: 2000-04-11 15:18:43
Document Modified: 2000-04-11 15:18:43

© 2024 FCC.report
This site is not affiliated with or endorsed by the FCC