Circuit Description

FCC ID: ALH30923140

Operational Description

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FCCID_64281

FCC ID:ALH30923140(TK—3107) FCC ID:ALH30923140(TK—3102) TK—3102/TK—3107 CIRCUIT DESCRIPTION The KENWOOD model TK—3102 and TK—3107 are UHF/FM hand—held transceivef designed to operate in the frequency range of 406 to 430MHz. The unit consists of a receiver, a transmitter, a phase—locked loop (PLL) frequency synthesizer, a digital control circuit, power supply circuit and a signaling circuit.TK—3107 is 16 Number of Channels, and TK—3102 Number of Channels. 1. RECEIVER CIRCUIT The receiver is double conversion superheterodyne, designed to operate in the frequency range of 406 to 430MHz. 1.1 FRONT—END RF AMPLIFIER An incoming signal from the antenna is applied to on RF amplifier (Q203) after passing through a transmit/receive switch cireuit (D102 and D103 are off) and a 3—pole LC filter. After the signal is amplified (Q203), the signal is filtered by a 3—pole LC filter to eliminate unwanted signals before it is passed to the first mixer. 1.2 FIRST MIXER The signal from the RF amplifier is heterodyned with the first local oscillator signal from the PLL frequency synthesizer circuit at the first mixer (Q202) to become a 38.85MHz first intermediate frequency (Ist IF) signal. The first IF signal is fed through two monolithic crystal filters (MCFs:XF200) to further remove spurious signals. 1.3 IF AMPLIFIER The first IF signal is amplified by Q201, and then enters IC200 (FM processing IC). The signal is heterodyned again with a second local oscillator signal within 1C200 to become a 450kHz second IF signal. The second IF signal is fed through a 450kHz ceramic filter to further eliminate unwanted signals before it is amplified and FM detected in 1C200. 1.4 AUDIO AMPLIFIER The recovered audio signal obtained from 1C200 is amplified by 1C300 (1/4) low pass—filter by 1C300(2/4) and high—pass filtered by Q300 (3/4) and Q300 (4/4), and de—empfasized by R303 and €306. The audio signal is then passed through an audio frequency switch (Q8303). The processed audio signal passes through an audio volume control and is amplified to a sufficient level to drive a loud speaker by an audio power amplifier (IC302). 1.5 SQUELCH AND MUTE CIRCUIT The output signal from the squelch circuit, which consists of IC200, is applied to the microprocessor. The microprocessor controls the mute control line (MUTE) according to the input signal and the microprocessor task condition. 2. TRANSMITTER 2.1 MICROPHONE CIRCUIT

FUC 1D:ALH30923140(TK—3107) FCC ID:ALH30923140(TK—3102) The signal from the microphone is high—pass filtered by IC500 (1/2), passed through microphone mute circuit (Q503), limited and pre—emphasized by IC500 (2/2). The signal component above the audio pass—band circuit is attenuated by splatter filter comprised of @501 and Q502. 2.2 MODULATOR CIRCUIT The output from the microphone amplifier passes through a variable resistor (VR501) for maximum deviation adjustment and is applied to a varactor diode (D5) in the voltage controlled oscillator (VCO) located in the frequencysynthesizer section. 2.3 DRIVER AND FINAL POWER AMPLIFIER CIRCUITS The transmit signal obtained from the VCO buffer amplifier Q100, is amplified to approximately 174Bm by Q101 and Q102. This amplified signal is passed to the power amplifier Q105 and Q107,which consists of a 2—stage FET amplifier and is capable of producing up to 4W of RF power. 2.4 TRANSMIT/RECEIVE SWITCHING CIRCUIT The power module output signal is passed through a low—pass filter network and a transmit/receive switching circuit before it is passed to the antenna terminal. The transmit/receive switching circuit is comprised of D101, D102 and D103. D100 is turned on (conductive) in transmit mode and turned off (isolated) in receive mode. 2.5 AUTOMATIC POWER CONTROL CIRCUIT AND TRANSMITTER OUTPUT LEVEL SWITCH The automatic power control (APC) circuit stabilizes the transmitter output power at a pre— determined level by sensing the collector current of the final amplifier Field effect transistor (FET). The voltage comparator IC100 (2/2) compares the voltage obtained by the above drain current with a reference voltage, set using the microprocessor and. An APC voltage proportional to the difference between the sensed voltage and the reference voltage appears at the output of 1C100 (1/2). This output voltage controls the gate of FET power amplifier, which keeps the transmitter output pevx/er constant. The transmitter output power can be varied by the microprocessor, which in turn changes the reference voltage and hence the output power. 3. PLL FREQUENCY SYNTHESIZER 8.1 PLL The frequency step of the PLL circuit is 5 or 6.25kHz. A 12.8MHz reference oscillator signal is divided at IC1 by a fixed counter to produce the 5 or 6.25kHz reference frequency. The VCO output signal is buffer amplified by Q2, then divided in IC1, by a dual—modules programmable counter in this case. The divided signal is compared in phase with the 5 or 6.25kHz reference signal in the phase comparator also in IC1. The output signal from the phase comparator is low—pass filtered and passed to the VCO to control the oscillator frequency. 8.2 VOLTAGE CONTROLLED OSCILLATOR (VCO)

FCC ID:ALH30923140(TK—3107) FCC ID:ALH30923140(TE—3102) The operating frequency is generated by Q4 in transmit mode and Q3 in receive mode. The oscillator frequency is controlled by applying the VCO control voltage, obtained from the phase comparator, to the varactor diodes (D2 and D4 in transmit mode and D1 and D3 in receive mode). The T/R pin is set high in receive mode causing Q5 and Q7 to turn off Q4, and turn on Q3, and is set low for transmit mode. The outputs from Q3 and Q4 are amplified by Q6 and outputted to the buffer amplifiers. 3.3 UNLOCK DETECTOR CIRCUIT If a pulse signal appears at the LD pin of IC1, an unlock condition occurs, the DC voltage, obtained from D7, R6 and C1, causes the voltage applied to the UL pin of the microprocessor to go low. When the microprocessor detects this condition, the transmitter is disabled by ignoring the push—to—talk switch input signal. 4. DIGITAL CONTROL CIRCUIT 4.1 KEY SWITCHES AND CHANNEL SELECTOR INPUT CIRCUIT The key switches and channel selector information are entered directly into the microprocessor (IC403). 4.2 RESET CIRCUIT When the power is initially turned on, IC400 detects a 5V reference voltage rise, then output a high level signal to reset the microprocessor (IC403). ’ 5. POWER SUPPLY CIRCUIT 5.1 POWER SWITCHING CIRCUIT A 5V reference voltage[5M] supply for the control circuit is derived from an internal battery by IC404. This reference is used to provide a 5V supply in transmit mode [5T], and a 5V supply in receive mode [5R)] and a 5V supply common in both modes [5C] based on the control signal sent from the microprocessor. 5.2 BATTERY SAVER CIRCUIT If no activity is detected (squelch closed) on the channel, the units enters into the battery save mode controlled by the microprocessor. In this mode, SAVE line is set low, causing Q406 to disable [5C] and [5M]. 6.ADDITIONAL CIRCUIT 6.1 QT, DQT ENCODE The QT, DQT encoder tone is set by the data from the microprocessor. QT, DQT tone is generated by the microprocessor (IC403). The output is applied to the VCO and TCXO (X1). 6.2 QT,DQT DECODE A part of the recovered audio signal obtained at the amplifier 1C300 (1/4) are the QT and DQT tones and are low pass filtered by 1C301 and passed to the microprocessor for decoding.


Document Created: 1999-10-15 11:52:49
Document Modified: 1999-10-15 11:52:49
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