Block Diagrams

FCC ID: AJL8221872

Block Diagram

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FCCID_283812

BLOCK DIAGRAMS – EXHIBIT D +3.3V ARINC 429 Outputs +3.3V IO DSP JTAG FLASH Bus SNOOPY 1 +1.5V CORE SNOOPY 2 JTAG PLD Conn SNOOPY Synth ASIC 1 BOARD_RST Tune FLASH R/W_F/CNTL 3.3V SPI Bus SERIAL EEPROM +3.3V -429 -CSDB DSP BUS FLASH -Discretes BNC (16 Bits) PROG/DATA -SPI Bus 16 +3.3V SYSTEM Disc IO (x16) STORAGE CLOCK 1M x 16 23.1 MHz CLK 4 GT28F160B3T80 CSDB (x2)) +/- 3 PPM 429 Inputs +3.3V Only Boot Block 8/16 bit wide Pwr Int NMI +15.0V (from PS) +3.3V +1.5V +5.0V TMS320vc5416 CORE DSP +3.3V To RF uPower 2.5V Synthesizers Regulator TPS76325DBVT +8.0V SPORT0 SPORT0 +8.0V DC 5.0V SPORT1 SPORT1 -8.0V Power +5.0V SPORT2 SPORT2 BD 5 Volt Regulator +28.0V IF Module RST LT1129IQ-5 Kick RST IF A/D FPGA IN +3.3V TPS3305-25 uP mon Analog A54SX32P-Q208I Spvr mon +3.3V 8 Ch, 8 BIT Outputs D/A Sport 1 AD8801 PS SYNC 2 x2 Ch, Bessel +3.3V 12 BIT FILTER x4 SPORT0 D/A and Gain Anti-Alias AD5322 2 x2 Ch, Audio 12 BIT FILTER XFMR Analog D/A and Gain (x2) FILTER AD5322 Analog Ser to Par FILTER Register File +3.3V Analog FILTER Analog Inputs Analog Parallel Monitored FILTER Signals 8 CH Analog FILTER A/D Analog (Baseband) 16-CH FILTER MAX146 Analog BIT PLD Mux Monitored Signals BIT MUX Microphone SWITCH CAP FILTER Input/Bias Figure # 1 – Controller/ Signal Processing Block Diagram

TO RCVR TO FROM 23.1 INPUT ANTENNA MHz TCXO I-Q PA -30 DB --30 DB T/R 8 POLE LP TX SYN. MOD SAMPLE COUPLER FILTER 118 MHz TO 136.993 MHz I Q PHASE_I FWD/REV SENSORS PHASE_Q LO RF LO φ I-Q ROTATE DEMOD RF FWD_PWR REV_PWR PHASE Q I ADJUST PA TEMP SENSOR Q_INPUT ERROR AMPS/ LOOP FILTERS PA TEMP I_INPUT Figure # 2 – Transmitter

TO SIMULCOMM THRESHOLD CONTROL SIMULCOMM HW CIRCUITS DETECTOR PRESELECTOR RECEIVER RF PRESELECTOR CONTROL #1 & #2 CONTROL #3 & #4 INPUT 118-153 MHz MAV-11 RF AMP 2 POLE FM BAND SIMULCOMM 2 POLE BP FILTER REJECT ATTN BP FILTER 118-137 MHz MAV 11 IF AMP 28.875 MHz 28.875 MHz FILTER MIXER RX SYNTHESIZER 146-166 MHz 2 STAGE AD603 IF AMPS 28.875 MHz IF OUTPUT TO A/D CONVERTER -5 dBm CARRIER FROM 23.1 MHz TCXO HW AGC DETECTOR VOICE/DATA FAST AGC Figure # 3 – Receiver Block Diagram

+28VDC PRIMARY PWR 28VDC_CLAMPED DC-DC 34 VOLT INPUT CONVERTER CLAMP FILTERING +8VDC_PSVP -8VDC_PSVP POWER WARN MONITOR FLYBACK +15VDC_PSVP +3.3VDC_PSVP CROWBAR ENERGY STORAGE/ MONITOR POWER UP/DOWN CONTROL PWM SHUTDOWN 3.3VDC MONITOR OVER VOLTAGE MONITOR 34 VOLT CLAMP SENSE CLAMP_ON _INT_F Figure # 4 – Power Supply Block Diagram


Document Created: 2002-11-15 12:28:21
Document Modified: 2002-11-15 12:28:21
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