Block Diagrams

FCC ID: AJL8221468

Block Diagram

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FCCID_183936

BLOCK DIAGRAMS – EXHIBIT D +3.3V ARINC 429 Outputs +3.3V IO DSP JTAG FLASH Bus SNOOPY 1 +1.5V CORE SNOOPY 2 JTAG Conn SNOOPY Synth PLD ASIC 1 BOARD_RST Tune FLASH R/W_F/CNTL 3.3V SPI Bus SERIAL EEPROM +3.3V -429 -CSDB DSP BUS FLASH -Discretes BNC (16 Bits) -SPI Bus PROG/DATA 16 +3.3V SYSTEM STORAGE Disc IO (x16) CLOCK 1Mx16 CLK 4 23.1MHz GT28F160B3T80 CSDB (x2)) +/-3PPM 429 Inputs +3.3VOnly Boot Block 8/16 bit wide Pwr Int NMI +15.0V (from PS) +3.3V +1.5V +5.0V TMS320vc5416 CORE DSP uPower +3.3V To RF 2.5V Regulator Synthesizers TPS76325DBVT +8.0V SPORT0 SPORT0 DC +8.0V 5.0V SPORT1 SPORT1 -8.0V Power +5.0V SPORT2 5 Volt SPORT2 BD Regulator +28.0V IF Module RST LT1129IQ-5 Kick RST IF A/D FPGA IN +3.3V TPS3305-25 uP mon Analog A54SX32P-Q208I Spvr mon +3.3V 8 Ch, 8 BIT Outputs Sport 1 D/A AD8801 PS SYNC 2x2 Ch, Bessel +3.3V 12 BIT SPORT0 FILTERx4 D/A andGain Anti-Alias AD5322 2x2 Ch, Audio 12 BIT FILTER XFMR Analog D/A andGain (x2) FILTER AD5322 Analog Ser to Par FILTER Register File +3.3V Analog FILTER Analog Inputs Analog Parallel Monitored FILTER Signals 8 CH Analog FILTER A/D Analog (Baseband) 16-CH FILTER MAX146 Analog BIT PLD Mux Monitored Signals BIT MUX Microphone SWITCH CAP FILTER Input/Bias Figure # 1 – Controller/ Signal Processing Block Diagram


Document Created: 2019-10-07 06:47:46
Document Modified: 2019-10-07 06:47:46
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