| File Name | Document Type | Date | Direct |
|---|
| user manual | Users Manual |
2010-06-23 00:00:00 |
pdf  |
| report | Test Report |
2010-06-23 00:00:00 |
pdf  |
| DAD external photo | External Photos |
2010-06-23 00:00:00 |
pdf  |
| ALADDIN external photo | External Photos |
2010-06-23 00:00:00 |
pdf  |
| label position | ID Label/Location Info |
2010-06-23 00:00:00 |
pdf  |
| label | ID Label/Location Info |
2010-06-23 00:00:00 |
pdf  |
| confidentiality letter | Cover Letter(s) |
2010-06-23 00:00:00 |
pdf  |
| block diagram of ALADDIN | Block Diagram |
2010-06-23 00:00:00 |
pdf  |
| authority to act IMQ | Attestation Statements |
2010-06-23 00:00:00 |
pdf  |
| ADC analog to digital conversion circuit | Schematics |
|
N/A |
| ALADDIN internal photos (confidentila) | Internal Photos |
|
N/A |
| Antenna multiplexer board | Schematics |
|
N/A |
| DAD functional scheme | Schematics |
|
N/A |
| DAD internal photos (confidential) | Internal Photos |
|
N/A |
| DAD service interface | Schematics |
|
N/A |
| PC interface LAN - WLAN | Schematics |
|
N/A |
| Power supply high voltage monitor | Schematics |
|
N/A |
| Power supply high voltage section +150 VDC | Schematics |
|
N/A |
| Power supply high voltage section -70 VDC | Schematics |
|
N/A |
| Power supply low voltage section | Schematics |
|
N/A |
| Receiver for HF dipole | Schematics |
|
N/A |
| technical description | Operational Description |
|
N/A |
| timing circuit | Schematics |
|
N/A |
| timing circuit control ection - CPLD | Schematics |
|
N/A |
| timing circuit control ection - CPU section | Schematics |
|
N/A |
| timing circuit front end | Schematics |
|
N/A |
| timing circuit Static RAM | Schematics |
|
N/A |
| Transmitter for HF dipole | Schematics |
|
N/A |
| trigger amplifier board | Schematics |
|
N/A |