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United States Patent | 6,480,800 |
Molyneaux , et al. | November 12, 2002 |
The invention is a method and apparatus that verifies the design of electronic circuitry containing a function to be tested. An input, such as a random input, is provided to the electronic circuitry containing the function, yielding an output. This output, in turn, is used as input (denominated "inverse input") to an inverse of the function to be tested. The resulting output (termed "inverse output") is compared to the original input to the function to be tested to facilitate verification of the design of the circuitry.
Inventors: | Molyneaux; Robert F. (Lakeway, TX), Raina; Rajesh (Austin, TX) |
Assignee: |
International Business Machines Corp.
(Armonk,
NY)
Motorola, Inc. (Schaumburg, IL) |
Appl. No.: | 09/246,896 |
Filed: | February 8, 1999 |
Current U.S. Class: | 702/120 ; 702/117; 716/106; 716/136 |
Current International Class: | G06F 19/00 (20060101); G06F 019/00 () |
Field of Search: | 702/117,124,57-59,66,70-74,108,126,182-185,186,189,FOR 103/ 702/FOR 104/ 702/FOR 110/ 716/5,6,1,4 703/13-16,20 714/738-742,732,735,736,718-720,722,723,724,728,48,49,54,57 324/73.1,765,763 365/201 |
5903475 | May 1999 | Gupte et al. |
6134684 | October 2000 | Baumgartner et al. |
6195616 | February 2001 | Reed et al. |