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United States Patent 3,662,329
Hill ,   et al. May 9, 1972
MULTI-PHASE TRAFFIC CONTROL SYSTEM

Abstract

The control system includes multi-phase solid state traffic controllers for controlling the operation of traffic signals in accordance with traffic demand. These controllers include phase selection circuitry for directly transferring a go signal activation for one phase to a second phase for which a go signal is called for by a traffic detector without first allocating a go signal activation to another phase in which a traffic detector is not calling, i.e., is not traffic actuated. Circuitry is also provided for preempting the operation of a controller to allocate a particular preselected pattern of traffic signals. Also, circuitry is provided to ensure that after operating power has been lost and restored consistent traffic signals will be activated for all traffic phases.

Inventors: Hill; Frank W. (Moline, IL), Bartlett; Peter G. (Davenport, IA), Clark; Larry K. (Davenport, IA)
Assignee: Gulf & Western Industries (New York, NY)
Appl. No.: 04/812,476
Filed: August 20, 1968

Current U.S. Class: 340/918
Current International Class: G08G 1/08 (20060101); G08G 1/07 (20060101); G08g 001/08 ()
Field of Search: 340/31,37

References Cited [Referenced By]
U.S. Patent Documents
3508192 April 1970 Brockett
3503041 March 1970 Du Vivier
Primary Examiner: Cooper; William C.
Claims


We claim:

1. In a traffic control system for controlling the operation of a traffic signal means displaying traffic signals including a go signal for each of at least three traffic phases, and wherein signal means for at least two of said phases are responsive to traffic having traffic detection means associated therewith for detecting traffic controlled by the signal means associated with such traffic detector; the improvement for transferring go signal activation from one of said phases to a phase associated with traffic detection means which has detected traffic, wherein said system comprises:

separate means for each phase for controlling activation of a go signal during that phase;

calling means for each such phase for providing a calling signal representative that traffic detection means of the associated phase is traffic activated;

a source of trigger pulses;

phase select counting means for counting said trigger pulses, said counting means having a plurality of output circuits which carry a pattern of output signals that changes in dependence upon the number of trigger pulses counted, said pattern of output signals being representative, at any one time, of conditions in a thoroughfare associated with one of said phases;

logic comparison means for comparing said pattern of output signals with said calling signals for providing a comparison signal when the said pattern of output signals is representative of the condition of the same thoroughfare that is represented by a said calling signal; and,

phase on activating means for activating the separate activatable means for the said same phase to control allocation of a go signal activation thereto, whereby a said go signal activation is directly transferred from one of said phases to another of said phases for which the detection means is actuated.

2. In a traffic control system as set forth in claim 1, count control means responsive to a said comparison signal to prevent said counting means from counting additional said trigger pulses.

3. In a traffic control system as set forth in claim 1, signal shifting means interposed between the output circuits of said counting means and said phase on activating means for applying signals to said phase on activating means representative of the pattern of output signals on the output circuits of said counting means when the last said comparison signal was provided.

4. In a traffic control system as set forth in claim 3, the improvement wherein said phase on activating means has a plurality of output circuits each coupled to one of said separate means for applying a phase on signal thereto for activating same and decoding means for decoding said representative signals and placing a said phase on signal on the decoder output circuit that is coupled to the separate means for the phase corresponding with that represented by the last pattern of output signals on the counting means output circuits.

5. In a traffic control system as set forth in claim 1, orientation programming means for activating each said calling means so that each said calling means provides a said calling signal.

6. In a traffic control system as set forth in claim 1, preemption control means for activating said phase on activating means to actuate a preselected one of said separate means.

7. In a traffic control system as set forth in claim 3, the improvement wherein said signal shifting means includes memory means having a plurality of input circuits coupled to the outputs of said phase select counting means and a plurality of output circuits coupled to said phase on activating means; shift logic means interposed between said phase select counting means and said memory means for applying signals to said memory means input circuits whereupon the output circuits of said memory means apply said representative signals to said phase on activating means.

8. In a traffic control system as set forth in claim 7, means for activating said shift logic means.

9. In a traffic control system as set forth in claim 7, preemption control circuit means coupled to the input circuits of said memory means for activating same so that said memory means output circuits carry a preselected pattern of signals, whereby said phase on activating means activates a preselected one of said separate means.

10. In a traffic controller for controlling the operation of signal light means displaying traffic signals including a go signal for each of at least three traffic phases, and wherein control for at least two of said phases is traffic activatable having traffic detection means associated therewith for detecting traffic in thoroughfares associated with such phases; the improvement comprising:

a common timer circuit associated with all of said phases and having a go timing means for timing a go interval;

timer control circuit means for each phase for controlling the duration said go timing means times a go interval; and

phase selection means for activating a said timer control circuit means associated with one of said phases for which detection means has been actuated, whereby a said go signal activation is directly transferred from one of said phases to the phase for which detection means has been actuated.

11. In a traffic controller as set forth in claim 10, calling means for each activatable phase for providing a calling signal representative that the associated phase is traffic activated.

12. In a traffic controller as set forth in claim 11, the improvement wherein said phase selection means includes:

a source of trigger pulses; and

phase select counting means for counting said trigger pulses, said counting means having a plurality of output circuits which carry a pattern of output signals that changes in dependence upon the number of trigger pulses counted, said pattern of output signals being representative, at any one time, of a particular one of said phases.

13. In a traffic controller as set forth in claim 11 logic comparison means for comparing said pattern of output signals with said calling signals for providing a comparison signal when said pattern of output signals is representative of the same activated phase that is represented by a said calling signal.

14. In a traffic controller as set forth in claim 13, phase on activating means for activating the timer control circuit means for the said phase represented by the last said pattern of output signals on the counting means output circuits.

15. In a traffic controller as set forth in claim 14, count control means responsive to a said comparison signal for preventing said counting means from counting additional said trigger pulses.

16. In a traffic controller as set forth in claim 14, signal shifting means interposed between the output circuits of said counting means and said phase on activating means for applying signals to said phase on activating means representative of the pattern of output signals on the output circuits of said counting means when the last said comparison signal was provided.

17. In a traffic controller as set forth in claim 16, the improvement wherein said phase on activating means has a plurality of output circuits each coupled to an associated one of said timer control circuit means for applying a phase on signal thereto activating, and decoding means for decoding said representative signals and placing a said phase on signal on the phase on output circuit that is coupled to the timer control circuit means for the phase corresponding with the phase represented by the last pattern of output signals on the counting means output circuits.

18. In a traffic controller as set forth in claim 11, orientation programming means for activating each said calling means so that each said calling means provides a said calling signal representative that the associated phase is traffic activated.

19. In a traffic controller as set forth in claim 14, including preemption control means for activating said phase on activating means to activate a preselected one of said timer control circuit means.
Description


The present invention relates to the art of traffic control and, more particularly, to controlling traffic flow in accordance with traffic demand.

The invention is particularly applicable to the art of traffic control and will be described with particular reference thereto; although it is to be appreciated that the invention has broader applications, such as in process controls for controlling energization of a plurality of loads.

Traffic controllers serve to control traffic signals which display go, caution, and stop signals to vehicles in thoroughfares representing traffic phases allocated to movements of traffic in such thoroughfares. Pretimed traffic controllers serve to control such traffic signals on a pretimed schedule. Actuated controllers, such as semi-actuated controllers or full actuated controllers, control such traffic signals in accordance with traffic demand as registered with the controllers by traffic detectors. A full actuated traffic controller has a detector associated with each phase and a semi-actuated controller has a detector associated with at least one, but not all, of the phases served by the controller.

Many actuated traffic controllers serve to control traffic signals at an intersection of three or more traffic phases, such as phases A, B, and C. If the controller is allocating a go signal to phase A, and phase C becomes traffic actuated, i.e., its associated detector has been actuated by a vehicle, then phase C is calling for allocation of a go signal. Some of the older traffic controllers would, in such a case as discussed, allocate a go signal to phase B, before allocating a go signal to the calling phase C. Since phase B was not traffic actuated, such an allocation of go time to phase B is an unnecessary waste of go time in a cycle of operation and may inhibit a smooth progressive flow of traffic through an intersection. A more efficient use of the traffic controller would be to directly transfer allocation of a go signal from phase A to calling phase C, without first awarding go time to phase B.

A traffic control system known in the prior art provides a phase selection circuit which serves, in the above example, to directly transfer a go signal from phase A to phase C. That system proposes that a timing module be used for each phase for controlling all timing operations for the traffic signals for that phase. A phase select circuit couples the modules in such a manner that a module associated with an actuated traffic phase will be conditioned to commence timing operations if it is the first so conditioned module in a series connected circuit to receive a phase selection signal. Such a system, for example, is disclosed in the Arthur E. Hilliker U.S. Pat. No. 3,191,148.

The present invention includes a traffic control system having an improved phase selection circuit for directly transferring a go signal activation from one phase to a phase associated with a traffic detector which has detected traffic. In accordance with this aspect of the invention, it is contemplated that a traffic control system be provided with signal light means for displaying traffic signals including a go signal for each of at least three traffic phases, and wherein signal control elements for at least two of the phases are traffic actuatable having traffic detection means associated therewith for detecting traffic in thoroughfares associated with such actuatable phases.

In accordance with one aspect of the present invention, an improvement is provided and includes a common timer circuit associated with all of the phases and having go timing means for timing a go interval; actuatable timer control circuit means for each phase for, when actuated, controlling the duration that the go timing means times a go interval; and, phase selection means for actuating an actuatable timer control circuit means associated with an actuated one of the traffic phases, whereby the go signal display is directly transferred from one of the phases to an actuated one of the phases.

In accordance with a still further aspect of the present invention, the improvement comprises separate actuatable means for each phase for, upon actuation, controlling allocation of a go signal display to that phase; calling means for each actuatable phase for providing a calling signal representative that the control for the associated phase is traffic actuated; actuatable phase selection counting means for counting trigger pulses obtained from a source of trigger pulses, with the counting means having a plurality of output circuits which carry a pattern of output signals that changes in dependence upon the number of trigger pulses counted, and that this pattern of output signals is representative at any one time of condition in one of the phases; logic comparison means for comparing the pattern of output signals with the calling signals for providing a comparison signal when the pattern of output signals is representative of the same actuated phase that is represented by a calling signal; and, phase on actuating means for actuating the separate actuatable means associated with the same actuated phase so as to control allocation of a go signal displayed thereto, whereby a go signal display is directly transferred from one of the phases to an actuated one of the phases.

In accordance with a still further aspect of the present invention, there is provided orientation programming means for actuating each calling means so that each of the calling means provides a calling signal representative that its associated phase is traffic actuated.

In accordance with a still further object of the present invention, there is provided preemption control circuit means for actuating the phase on actuating means to, in turn, actuate a preselected one of the actuatable timer control circuit means.

The primary object of the present invention is to provide an improved traffic control system incorporating solid state components so as to thereby minimize maintenance and power requirements for economy of operation.

Another object of the present invention is to provide an improved solid state multiphase traffic actuated controller.

A still further object of the present invention is to provide an improved phase select circuit for directly transferring allocation of go signals from one phase to an actuated phase.

A still further object of the present invention is to provide an improved traffic controller having a preemption control circuit for preempting the operation of the controller to allocate a particular preselected pattern of traffic signals.

A still further object of the present invention is to provide an improved traffic controller having orientation programming circuit means to ensure that after operating power has been lost and restored all of the traffic phases will be sequentially allocated traffic signals.

These and other objects and advantages of the invention will become apparent from the following description of the preferred embodiments of the invention as read in connection with the accompanying drawings in which:

FIG. 1 is a schematic illustration of the invention as applied to a traffic control system incorporating a four phase, full actuated traffic controller;

FIG. 2 is a combined schematic-block diagram illustration of the four phase, full actuated traffic controller;

FIG. 3 is a schematic illustration of the timer circuit found within FIG. 2;

FIG. 4 is a schematic illustration of load control circuitry coupled to FIG. 2;

FIG. 5 is a combined schematic block diagram illustrating the phase select circuitry in greater detail than that shown in FIG. 2;

FIG. 6 is a schematic illustration of the phase select logic circuitry shown in block diagram in FIG. 5;

FIG. 7 is a schematic illustration of the call on the other side logic circuitry shown in block diagram in FIG. 5;

FIG. 8 is a schematic illustration of the phase on logic circuitry illustrated in block diagram in FIG. 5;

FIG. 9 is a schematic illustration of the select stop logic circuitry illustrated in block diagram in FIG. 5;

FIG. 10 is a combined schematic block diagram illustration of a second embodiment of the invention;

FIG. 11 is a schematic illustration of circuitry used with the embodiment shown in FIG. 10;

FIG. 12 is a schematic illustration of preemption control circuitry; and,

FIG. 13 is a schematic illustration of orientation programming circuitry.

Referring now to the drawings, wherein the showings are for purposes of illustrating the preferred embodiments of the invention and not for the purposes of limiting same, FIG. 1 illustrates one application of the invention as applied to a four phase, full actuated traffic controller LC-1, which is more specifically illustrated in FIGS. 2 through 9. This controller serves to allocate and time go and caution signals to traffic phases A, B, C, and D. Each of these traffic phases is traffic actuated; to wit, each includes a traffic detector. Thus, phase A includes detectors D1 and D2, phase B includes detectors D3 and D4, phase C includes detector D5, and phase D includes detectors D6 and D7. In one form, each detector may be a spot detector, such as the familiar treadle pad which provides a momentary pulse each time a vehicle is detected. Alternatively, the detectors may take the form of presence detectors which may be used in a counting operation for providing a pulse for each detected vehicle. It is also contemplated that the detectors may take the form of true presence detectors which provide a presence signal so long as a vehicle is present within a zone of influence. Such presence dtectors may be either loop detectors or ultrasonic detectors, both of which are well known to those skilled in the art.

LOCAL CONTROLLER GENERAL DESCRIPTION

Reference is now made to FIG. 2, which is a combined schematic block diagram illustration of the local controller LC-1 for controlling the operation of signal light S to display go and caution signals for each of the traffic phases A, B, D, and D. The local controller LC-1 generally comprises: a common timer circuit T associated with all of the traffic phases and which includes a go timer T1, and a caution timer T2; a common traffic interval sequencer circuit IS; a phase A timer control circuit TC-1; a phase B timer control circuit TC-2; a phase C timer control circuit TC-3 and a phase D timer control circuit TC-4; and, a phase on select circuit PS.

TIMER CONTROL CIRCUITS

Timer control circuits TC-1, TC-2, TC-3, and TC-4 are substantially identical to each other and, accordingly, like components are identified with like character references for simplifying the description of the invention. The description that follows is given with particular respect to timer control circuit TC-1. As shown in FIG. 2, timer control circuit TC-1 includes an NPN-transistor 10 having its collector connected to a B+ power supply source and its emitter connected to a go timing potentiometer 12, and to a caution timing potentiometer 14. As shown, these two potentiometers have their resistance portions connected together in parallel between ground and the emitter of transistor 10. The wiper arm of potentiometer 12 is coupled through a diode 16, poled as shown, to timer circuit T1. Similarly, the wiper arm of potentiometer 14 is connected through a diode 18, poled as shown, to timer circuit T2. It will be noted that timer control circuits TC-1 through TC-4 are connected together in parallel and, in the event the controller serves to control more than four traffic phases, the additional timer control circuits will also be connected in parallel with timer control circuits TC-1 through TC-4. Briefly, whenever transistor 10 in timer control circuit TC-1 is actuated into conduction, essentially B+ potential is applied across the resistance portions of potentiometers 12 and 14. The wiper arms on these two potentiometers are adjusted, as desired, to provide voltages for application to timer circuits T1 and T2, which voltages respectively control the time duration that these two timers perform their timing functions.

COMMON TIMER CIRCUITS

The common timer circuit T incorporates a go timer T1 and a caution timer T2, having their inputs respectively coupled to the commonly connected outputs of go and caution timing potentiometers 12 and 14 in the timer control circuits TC-1 through TC-4. In addition, another input to timer T1 and to timer T2 is obtained from an output circuit g of sequencer circuit IS. Another input to timer T1 is taken from an output circuit y of sequencer circuit IS.

Reference is now made to FIG. 3 which schematically illustrates timer circuits T1 and T2. As shown there, timer circuits T1 and T2 are substantially identical and, accordingly, like components are identified with like reference numbers. The description which follows is specifically given with reference to timer circuit T1. As shown, timer circuit T1 includes an NPN-transistor 20 having its base connected to output circuit y of sequencer IS and its emitter connected to ground. The collector to emitter circuit of transistor 20 is connected in parallel with a timing capacitor 22. The junction of the collector of transistor 20 and one side of capacitor 22 is connected through a timing resistor 24 to a B+ voltage supply source. Capacitor 22 is coupled to a comparator circuit in the form of a differential amplifier, including NPN-transistors 26 and 28, having their emitters connected together in common and thence through a resistor 30 to ground. The collectors of transistor 26 and transistor 28 are respectively connected through resistors 32 and 34 to the B+ voltage supply source. The base of transistor 28 is connected to the commonly connected cathodes of diodes 16 in timer control circuits TC-1 through TC-4. The collector of transistor 28 is connected to the input of a timer memory circuit TM. This timer memory circuit includes two NOR-gates 36 and 38 connected together to define a two input, bistable multivibrator circuit. One input to the timer memory circuit is taken from the collector of transistor 28 and is applied to the input of NOR-gate 36. The second input to the timer memory circuit TM is taken from output circuit g of sequencer IS, through a capacitor 40, and thence to one input of NOR-gate 38. The output of NOR-gate 38 serves as the output of the timer memory circuit TM and is applied (as shown in FIG. 2) to an input terminal T1' of the phase select circuit PS, as well as to one input of an AND-gate 42.

Timer circuit T2 differs from timer circuit T1 only inasmuch as the base of transistor 20 is connected to the output circuit g of sequencer circuit IS and that the base of transistor 28 is connected to the commonly connected cathodes of diodes 18 in the timer control circuit TC-1 through TC-4. Also, the output of NOR-gate 38 in timer circuit T2 is connected (as shown in FIG. 2) to terminal T2' of phase select circuit PS as well as to the interval sequencer circuit IS.

DETECTOR MEMORY CIRCUITS

Reference is now made to FIG. 2, which illustrates detector memory circuits AM, BM, CM, and DM, which are respectively associated with phases A, B, C, and D for remembering traffic actuations taking place in those phases. Detector memory circuit AM includes a pair of NOR-gates 44 and 46 connected together to define a two input bistable multivibrator circuit. The input to NOR-gate 44 is taken from the output of a NOR-gate 48, having its input connected through a resistor 50 to a B+ voltage supply source. The input to NOR-gate 48 is also connected through a normally open switch DA to ground. Switch DA is a simplified showing of detectors D1 and D2 associated with phase A and serves, when a vehicle is detected in phase A, to become closed to apply a ground potential or binary "0" signal to the input of NOR-gate 48.

In a manner similar to that as described above, the detector memory BM includes NOR-gates 52 and 54 connected together to define a bistable multivibrator circuit. NOR-gate 56 is connected to the input of NOR-gate 52. The input to NOR-gate 56 is taken through a resistor 58 to the B+ voltage supply source as well as through a normally open switch DB, representative of phase B traffic detectors D3 and D4.

Detector memory CM takes the form of a pair of NOR-gates 60 and 62 connected together to define a bistable multivibrator circuit. The input to NOR-gate 60 is taken from the output of a NOR-gate 64 having its input connected through a resistor 66 to a B+ voltage supply source, as well as through a normally open switch DC to ground. Normally open switch DC is a simplified illustration of detector D5 associated with a phase C.

Detector memory DM includes a pair of NOR-gates 68 and 70 connected together to define a bistable multivibrator circuit. The input to NOR-gate 70 is taken from the output of a NOR-gate 72 having its input connected through a resistor 74 to a B+ voltage supply source as well as through a normally open switch DD to ground. Normally open switch DD is a simplified illustration of phase D detectors D6 and D7.

The outputs of NOR-gates 46, 54, 62, and 68 are respectively coupled to input terminals AM', BM', CM', and DM' in the phase select circuit PS. Also, the phase select circuit PS has four output circuits a, b, c, and d which are respectively coupled to the inputs of NOR-gates 46, 54, 62, and 68.

INTERVAL SEQUENCER CIRCUIT

The inverval sequencer circuit IS serves to control the sequence of the intervals to be allocated and timed for each traffic phase. Thus, within any particular phase, the sequencer serves to ensure that when, for example, the phase A operation commences, the timer T1 completes its timing function before timer T2 commences its timing function. The sequencer circuit IS may take various forms and, as shown in FIG. 2, it includes two NOR-gates 80 and 82 connected together to define a two input bistable multivibrator circuit. One input to NOR-gate 80 is taken from the output of AND-gate 42. Also, one input of NOR-gate 82 is taken directly from the output of NOR-gate 38 in the caution timer circuit T2. The output of NOR-gate 80 is connected to an output circuit g. Similarly, the output of NOR-gate 82 is connected to output circuit y.

SIGNAL LIGHT CONTROL CIRCUITS

Reference is now made to FIG. 4 which illustrates a signal light control circuit to be used for energizing go, caution, and stop signal lights associated, for example, with phase A. This circuit is described with respect to phase A; however, it should be appreciated that a similar circuit may be used for phases B, C, and D. As shown in FIG. 4, the control circuit serves to energize the phase A green light AG, or the phase A yellow light AY, or the phase A red light AR. The circuit includes NOR-gates 90, 92, and 94 having their inputs respectively coupled to output circuit a of the phase select circuit PS and to output circuits g and y of the interval sequencer circuit IS. The two inputs of NOR-gate 94 are respectively connected to the outputs of NOR-gates 90 and 92. The inputs of NOR-gate 98 are respectively connected to the outputs of NOR-gates 90 and 94. The output of NOR-gates 96 and 98 are coupled to the inputs of a NOR-gate 100. Also, the outputs of NOR-gates 96, 98, and 100 are respectively coupled to load switches LS-1, LS-2 and LS-3. These load switches may, for example, take the form of triacs having their gates connected to the outputs of the associated NOR-gates 96, 98, and 100. As is well known, once a positive signal is applied to the gate of such a triac, the triac is gated into conduction for purposes of switching an alternating current voltage source across a load. Alternating load current source V is coupled to each of the load switches LS-1, LS-2, LS-3 which, when gated into conduction by their respective NOR gates, serve to couple the voltage source across the selected signal light AG, AY, or AR.

GENERAL OPERATION OF CONTROLLER

Before describing the specific circuitry of the phase select circuit PS shown in block diagram form in FIG. 5 and in greater detail in FIGS. 6, 7, 8, and 9, a description of the operation of the local controller LC-1 described thus far is presented. Briefly, whenever a right-of-way signal is allocated to a particular phase, such as phase A, the common go timer T1 is actuated to time a period of time as adjusted by potentiometer 12 in the timer control circuit TC-1. Once timer T1 has completed its timing function, the phase select circuit PS serves to determine whether any of the other phases are traffic actuated; to wit, whether any of the detectors associated with traffic phases B, C, and D has detected a vehicle. Once this determination has been made, an output signal is placed on select stop terminal SS (see FIG. 2). Since timer circuit T1 has timed out and a positive signal is obtained from select stop terminal SS, a binary "1" signal is obtained from the output of AND-gate 42. Depending upon which phase B, C, or D is selected, output circuits b, c, or d will be energized to carry a positive signal; to wit, a binary "1" signal.

In operation of the controller it may be assumed that output circuit a of phase select circuit PS is energized to provide a phase on signal. This is a positive or binary "1" signal which serves to forward bias transistor 10 in timer control circuit TC-1 into conduction. Thus, potentiometers 12 and 14 in timer control circuit TC-1 apply control potentials to timer circuits T1 and T2 in the common timer T. During the previous traffic interval the output circuit y of sequencer circuit IS provided a positive potential to forward bias transistor 20 (see FIG. 3) into conduction to short circuit timing capacitor 22 in timer circuit T1. However, when timer circuit T2, during that previous interval, completed its timing function the output circuit y, which is connected to the output of NOR-gate 82, became a binary "0" signal or ground potential, therefore removing this short circuit. Accordingly, during the phase A operation timer circuit T1 commences to time by permitting capacitor 22 to charge toward the B+ potential. Since the base of transistor 28 is coupled to potentiometer 12 in timer control circuit TC-1, a potential as determined by the adjustment of the wiper arm of potentiometer 12 is applied between ground and the base of transistor 28. When the voltage stored by capacitor 22 exceeds that applied between ground and the base of transistor 28, transistor 28 will be reverse biased and a positive, i.e., a binary "1," signal is applied to the input of NOR-gate 36 in the timer memory circuit TM. Thus, the output of NOR-gate 36 becomes a binary "0" signal, causing the output of NOR-gate 38 to become a binary "1" signal. This binary "1" signal is applied to terminal T1' in the phase select circuit PS, as well as to one input of AND-gate 42. The phase select circuit now commences its phase selection operation and once it has determined which phase, B, C, or D, will next be allocated a right-of-way signal, the select stop circuit SS is energized to apply a second binary "1" signal to the input of AND-gate 42. Accordingly, AND-gate 42 now applies a binary "1" signal to the input of NOR-gate 80 in the interval sequencer circuit IS. This forces the output of NOR-gate 80 to be changed to a binary "0" level, deenergizing output circuit g. Also, the output of NOR-gate 82 now carries a binary "1" signal, energizing output circuit y.

Referring now to FIG. 3, since output circuit y is energized to carry a binary "1" signal, transistor 20 in timer circuit T1 is forward biased to maintain that timer reset by short circuiting capacitor 22. Since output circuit g is now deenergized, the short circuit is removed from transistor 20 in timer circuit T2. Accordingly, timer circuit T2 operates in the same fashion as described above with respect to timer circuit T1 and once the circuit has completed its timing function, it provides a binary "1" signal at the output of NOR-gate 38 in timer circuit T2 and this signal is applied to terminal T2' in the phase select circuit PS, as well as to one input of NOR-gate 82 in the interval sequencer circuit IS. Application of this binary "1" signal to the input of NOR-gate 82 causes the sequencer circuit IS to revert to its original condition, wherein the output terminal g is energized and the output terminal y is deenergized.

During the phase A operation, described above, the output circuit a of the phase select circuit PS is energized and at different times output circuits g and y of the sequencer circuit IS are energized. Reference is now made to FIG. 4 from which it will be noted that during the period that output circuits a and g are both energized, the outputs of NOR-gates 90 and 92 carry binary "0" signals, whereupon the output of NOR-gate 96 applies a positive or binary "1" signal to trigger load switch LS-1 into conduction so that the alternating current voltage source V is applied to energize the phase A green light AG. When the output g of sequencer circuit IS is deenergized, light AG is deenergized. When sequencer output circuit y becomes energized during the period that output circuit a is energized, then the output of NOR-gate 98 carries a binary "1" signal for actuating load switch LS-2 into conduction to energize the phase A yellow light AY. Whenever terminals g and y are both deenergized, or whenever either of these are energized, but output circuit a of the phase select circuit is not energized, then NOR-gates 96 and 98 carry binary "0" signals, causing NOR-gate 100 to apply a binary "1" signal to actuate load switch LS-3 into conduction to energize the phase A red light AR.

Having now provided a description of the operation of local controller LC-1, attention is specifically directed to the phase select circuit PS shown in FIGS. 5 through 9.

PHASE SELECT CIRCUIT

Reference is now made to FIG. 5, which presents a combined schematic block diagram illustration of the phase selection circuit PS shown as a single block diagram in FIG. 2. As shown in FIG. 5, the phase select circuit generally comprises a phase select logic circuit PSL; a call on the other side logic circuit COS; a phase select search circuit PSS, including a phase next ring flip-flop FF-3 and a phase next barrier flip-flop FF-4; a shift logic circuit SL; a phase on next flip-flop FF-5; a phase on next barrier flip-flop FF-6; a phase on logic circuit POL and a select stop logic circuit SSL. Circuits PSL, COS, POL, and SSL are illustrated in greater detail in FIGS. 6, 7, 8, and 9, respectively.

PHASE SELECT LOGIC CIRCUIT

Referring now to FIG. 6, the phase select logic circuit PSL includes an alternating current voltage source V coupled between ground and a wave shaper WS, having its output circuit connected to ground through a diode 110, poled as shown, so as to provide a plurality of positive trigger pulses P1, P2, etc., which are shaped as square waves of the same amplitude and duration and are of a fixed frequency, such as one pulse per second. The output of wave shaper WS is applied to trigger terminal T of flip-flop FF-3 in the phase select search circuit PSS (FIG. 5). Input terminal T1' of the phase select logic circuit PSL is connected to the input of a NOR-gate 112 having its output connected to the input of a NOR-gate 114. A second input to NOR-gate 114 is taken from the select stop terminal SS of the select stop logic circuit (FIG. 9). The output of NOR-gate 114 is coupled through a NOR-gate 116 to the input of a NOR-gate 118. A second input to NOR-gate 118 is taken from the "0" output terminal of flip-flop FF-3 in the phase select search circuit PSS. The output of NOR-gate 118 is applied as one input to a NOR-gate 120. The second input to NOR-gate 120 is taken from the "0" terminal of flip-flop FF-3, and a third input to NOR-gate 120 is taken from the input terminal y'. NOR-gate 122 has its input connected through a resistor 124 to ground, as well as to the output of the call on other side logic circuit COS (FIG. 7). The output of NOR gate 122 is applied as a fourth input to NOR-gate 120. The output of NOR-gate 120 is applied as one input to a NOR-gate 123,having a second input taken from the output of NOR-gate 116. The output of NOR-gate 123 is taken through NOR-gate 125 to terminal C of flip-flop FF-3 in the phase select search circuit PSS. The output of NOR-gate 118 is applied to the input of a NOR-gate 126. The output of NOR-gate 126 in turn is applied to the input of a NOR-gate 128 having a second input taken from the output of NOR-gate 122. The output of NOR-gate 128 is applied through a NOR-gate 130 to terminal c' of flip-flop FF-4 in the phase select search circuit PSS.

CALL ON OTHER SIDE LOGIC

Reference is now made to FIG. 7 which schematically illustrates the call on other side logic circuit COS which is shown in block diagram form in FIG. 5. This circuit includes a pair of NOR-gates 140 and 142. NOR-gate 140 has its input connected to terminal "1" of flip-flop FF-4 in phase select search circuit PSS. NOR-gate 142 has two inputs, one taken from the input terminal AM' and the other taken from the input terminal BM'. The outputs of NOR-gates 140 and 142 are connected to the inputs of a NOR-gate 144 having its output connected through a diode 146, poled as shown. The circuit also includes a second pair of NOR-gates 148 and 150. NOR-gate 148 has its input taken from output terminal "0" of flip-flop FF-4 in phase select search circuit PSS. NOR-gate 150 has two inputs respectively taken from input terminals CM' and DM'. The outputs of NOR-gates 148 and 150 are connected as the inputs to a NOR-gate 152 having its output connected through a diode 154, poled as shown, Diodes 146 and 154 are connected together, as shown, with the output of the circuit connected to the input of NOR-gate 122 in the phase select logic circuit shown in FIG. 6.

PHASE SELECT SEARCH CIRCUIT PSS

Referring now to FIG. 5, the phase select search circuit PSS includes a phase next ring flip-flop FF-3 and a phase next barrier flip-flop FF-4. The internal circuitry of each flip-flop does not form a part of the invention herein and many varied circuits could be used. One circuit which may be used as a flip-flop is one half of a Motorola integrated circuit, Model MC 790P, or the equivalent. Conventionally, such a flip-flop is labeled with output terminals "1," "0" for the two stable states of the flip-flop, together with a label S for the set input terminal, label C for the clear input terminal, and label T for the trigger input terminal. As shown, the set S and clear C terminals of each flip-flop are connected together in common. The common connection for flip-flop FF-3 is connected to the output of NOR-gate 125 in the phase select logic circuit PSL. Similarly, the common connection of flip-flop FF-4 is connected to the output of NOR-gate 130 of the phase select logic circuit PSL. The input trigger terminal T of flip-flop FF-3 is connected to the output of wave shaper WS in the phase select logic circuit PSL. Upon receipt of the trailing negative going edge of pulses P1, P2, etc., taken from the output of wave shaper WS, flip-flop FF-3 changes from one stable state to the other. Output terminal "1" of flip-flop FF-3 is connected to the input trigger terminal T of flip-flop FF-4.

SHIFT LOGIC CIRCUIT

Reference is now made to FIG. 5 which illustrates the shift logic circuit SL. As shown in FIG. 5, the circuit includes NOR-gates 160, 162, 164, 166, 168. Each of these NOR gates has one input connected to the output of a NOR-gate 170 having its input connected to input terminal T2'. The output of NOR-gate 160 is connected to one input of the phase on logic circuit POL. A second input of NOR-gate 162 is taken from output terminal "1" of flip-flop FF-3 and the output of this NOR gate is connected to the phase on next flip-flop FF-5. A second input of NOR-gate 164 is connected to output terminal "0" of flip-flop FF-3 and the output of this NOR gate is connected to the phase on next flip-flop FF-5. One input of NOR-gate 166 is connected to output terminal "1" of flip-flop FF-4 and the output of this NOR gate is connected to the phase on barrier flip-flop FF-6. Similarly, one input of NOR-gate 168 is connected to output terminal "0" of flip-flop FF-4 and the output of this NOR gate is connected to the phase on barrier flip-flop FF-6.

FLIP-FLOPS FF-5, FF-6

As shown in FIG. 5, the phase on next flip-flop FF-5 includes a pair of NOR-gates 180 and 182 connected together to define a two input bistable multivibrator circuit. The input to NOR-gate 180 is taken from the output of NOR-gate 162 and the input to NOR-gate 182 is taken from the output of NOR-gate 164. The outputs of NOR-gates 180 and 182 are connected to the phase on logic circuit POL. The phase on barrier flip-flop FF-6 is similar to flip-flop FF-5 and includes a pair of NOR-gates 184 and 186 connected together to define a two input bistable multivibrator circuit. The input to NOR-gate 184 is taken from the output of NOR-gate 166 and the input to NOR-gate 186 is taken from the output of NOR-gate 168. The outputs of NOR-gates 184 and 186 are connected to the phase on logic circuit POL.

PHASE ON LOGIC

Reference is now made to FIG. 8 which provides a schematic illustration of the phase on logic circuit POL. As shown in FIG. 8, this circuit includes a pair of NOR-gates 190 and 192. NOR-gate 190 has two inputs, one being connected to the output of NOR-gate 160 in the shift logic circuit SL, and the other being connected to the output of NOR-gate 182 in flip-flop FF-5. Similarly, NOR-gate 192 has two inputs, one being connected to the output of NOR-gate 160 and the other being connected to the output of NOR-gate 180 in flip-flop FF-5. The outputs of NOR-gates 190 and 192 are connected to the inputs of NOR-gates 194 and 196, respectively. NOR-gates 198 and 200 have their inputs respectively connected to the outputs of NOR-gates 184 and 186 in the phase on barrier flip-flop FF-6. NOR-gate 202 has two inputs, one being taken from the output of NOR-gate 194 and the other being taken from the output of NOR-gate 198. Similarly, NOR-gate 204 has two inputs, one being taken from the output of NOR-gate 196 and the other being taken from the output of NOR-gate 198. NOR-gate 206 has one input taken from the output of NOR-gate 196 and the other input taken from the output of NOR-gate 200. Also, NOR-gate 208 has one input taken from the output of NOR-gate 194 and the other being taken from the output of NOR-gate 200. The outputs of NOR-gates 206, 208, 204, and 202 are respectively connected to output terminals a, b, c, and d of the phase selection circuit (see FIG. 2).

SELECT STOP LOGIC

The select stop logic circuit is more particularly illustrated in FIG. 9, and includes four NOR-gates 210, 212, 214, and 216. The inputs to NOR-gates 210 and 212 are respectively taken from the "1" and "0" output terminals of flip-flop FF-3. Similarly, the inputs to NOR-gates 214 and 216 are respectively taken from the "1" and "0" outputs of flip-flop FF-4. The select stop logic circuit also includes NOR-gates 218, 220, 222, and 224 having their inputs respectively connected to terminals AM', BM', CM' and DM'. The circuitry also includes NOR-gates 226, 228, 230, and 232. NOR-gate 226 has four inputs respectively taken from output terminal a, the output of NOR-gate 210, the output of NOR-gate 216 and the output of NOR-gate 218. Similarly, NOR-gate 228 has four inputs respectively taken from output terminal b, the output of NOR-gate 212, the output of NOR-gate 216, and the output of NOR-gate 220. Also, NOR-gate 230 has four inputs respectively taken from output circuit c, the output of NOR-gate 210, the output of NOR-gate 214 and the output of NOR-gate 222. Further, NOR-gate 232 has four inputs respectively taken from the output circuit d, the output of NOR-gate 212, the output of NOR-gate 214, and the output of NOR-gate 224. The outputs of NOR-gates 226, 228, 230, and 232 are respectively connected through diodes 234, 236, 238, and 240 and thence connected together in common to output terminal SS.

PHASE SELECTION GENERAL DESCRIPTION

The following is a generalized description of the phase selection operation with reference to FIGS. 2 and 5. This description is given in a functional manner and a more detailed description will follow with reference to FIGS. 6, 7, 8, and 9.

Once a phase has been selected to which control of allocation of a right-of-way signal will be transferred, this information is shifted by means of the shift logic circuit SL to the flip-flops FF-5 and FF-6. This information, in turn, is decoded by the phase on logic circuit POL and one of its outputs a, b, c, or d will be energized in accordance with which phase is to receive the control of allocation of a right-of-way interval.

The phase selection itself is accomplished by the phase select logic circuit PSL working in conjunction with the phase select search circuit PSS. The flip-flops FF-3 and FF-4 in phase select search circuit PSS receive input information from the phase select logic circuit PSL. When one of the detector memories AM, BM, CM, or DM (FIG. 2), is actuated, this condition is decoded by the call on other side logic circuit COS to provide an output or calling signal to the phase select logic circuit PSL. This information, together with the information taken at input terminals T1', Y1', and from the select stop logic circuit SL, are decoded by phase select logic circuit PSL to actuate the phase select search circuit PSS. Once the searching function has been completed this is noted by the select stop logic circuit SSL which sends a command back to the phase select logic circuit PSL to stop further searching operations.

A portion of the theory of operation involves a discussion of the term known as "Barrier." Traffic phases A and B will be considered as the phases on the left side of the barrier, and traffic phases C and D will be considered as the phases on the right side of the barrier. Each side of the barrier, in turn, has left and right sides. On the left side of the barrier phases A and B are respectively the left and right sides. On the right side of the barrier phases C and D are respectively the left and right sides. If controller LC-1 is displaying a right-of-way signal to phase A and the controller determines that phase B desires right-of-way, then the operation which ensues takes place on the same side of the barrier. If a detector call indicated that phase D (on the opposite side of barrier) is traffic actuated, then the phase next barrier flip-flop FF-4 will perform a portion of the phase select search operation.

Once the correct phase has been determined further searching is stopped by the select stop logic circuit SSL. The information is then held until the yellow timer T2 completes its timing function. At that point, the shift logic circuit SL is actuated so that the information in the phase select search circuit PSS is shifted from flip-flops FF-3 and FF-4 to flip-flops FF-5 and FF-6. The outputs of these flip-flops contain the correct information as to which phase should be allocated the next right-of-way interval. This information is decoded by the phase on logic circuit POL to energize the appropriate phase on terminal a, b, c, or d.

SAME SIDE OF BARRIER OPERATION

It may be assumed that phase A is being allocated a right-of-way signal and that a traffic actuation has taken place in phase B. Also, it may be assumed that after phase A has been allocated a right-of-way signal, timer T1 has completed its timing function and has provided a binary "1" output signal to input terminal T1' of the phase select circuit as well as to one input of AND-gate 42. Since phase B is traffic actuated, normally open switch DB was at least momentarily closed. The momentary closure applied a binary "0" signal to the input of NOR-gate 56 (FIG. 2). Accordingly, NOR-gate 56 applied a binary "1" signal to the input of detector memory BM, the output of which applies a binary "1" signal to terminal BM' of the phase select circuit.

Referring now to FIGS. 5 and 7, it will be noted that the call on other side circuit receives a binary "1" signal at its input terminal BM'. Accordingly, the output of NOR-gate 142 applies a binary "0" signal to the input of NOR-gate 144. A second input to NOR-gate 144 is taken from the output of NOR-gate 140. The input to NOR-gate 140 is taken from output terminal "1" of flip-flop FF-4. During operation on the left side of the barrier, which involves phases A and B, output terminal "1" of flip-flop FF-4 carries a binary "0" signal. Accordingly, the output of NOR-gate 140 is a binary "1" signal. Thus, the output of NOR-gate 144 carries a binary "0" signal.

Since during this operation, the "0" terminal of flip-flop FF-4 carries a binary "1" output signal, the output of NOR-gate 148 is a binary "0" signal. Since no traffic has been detected in phases C and D, input terminals CM' and DM' carry binary "0" signals. Thus, NOR-gate 150 applies a binary "1" signal to the input of NOR-gate 152. Since the output circuits of NOR-gates 144 and 152 carry binary "0" signals, a binary "0" signal is applied to the input of NOR-gate 122 in the phase select logic circuit (FIG. 6).

The output circuit of NOR gate 122 applies a binary "1" signal to the input of NOR-gate 120, as well as to the input of NOR-gate 128. Thus, the output of NOR-gate 128 carries a binary "0" signal causing the output of NOR-gate 130 to apply a binary "1" signal to the clear terminal C of flip-flop FF-4 to hold that flip-flop from being actuated from one stable state to the other.

When timer T1 completes its timing function, it applies a binary "1" signal to input terminal T1' of the phase select circuit PS. Accordingly, NOR-gate 112 in the phase select logic circuit PSL receives a binary "1" signal at its input circuit, whereupon its output circuit applies a binary "0" signal to the input of NOR-gate 114. Since searching operations have not been completed, a binary "0" signal is present on the select stop terminal SS. Thus, NOR-gate 114 applies a binary "1" signal to NOR-gate 116, the output of which applies a binary "0" signal to one input of NOR-gate 123. Since, as stated hereinbefore, a binary "1" signal is applied from the output of NOR-gate 122 to the input of NOR-gate 120, a second binary "0" signal is applied to the second input of NOR-gate 123. Thus, NOR-gate 123 applies a binary "1" signal to the input of NOR-gate 125. The output of NOR-gate 125, in turn, now applies a binary "0" signal to the clear terminal C of flip-flop FF-3 to permit that flip-flop to be actuated from one stable state to the other upon receipt of the trailing edge of the first pulse at its input trigger terminal T from wave shaper WS.

With a binary "0" signal being applied to terminal C of flip-flop FF-3, the strobe signal, i.e., the negative going trailing edge of the first received pulse from wave shaper WS, serves to trigger the flip-flop from one stable state to the other. If as assumed, the controller was allocating a right-of-way signal to phase A, then a binary "1" signal is carried by the "0" terminal of flip-flop FF-3. Accordingly, upon receipt of the first trigger pulse, the flip-flop FF-3 is actuated so that only its "1" terminal carries a binary "1" signal. This binary "1" signal is applied to the select stop logic circuit SSL which will determine by a comparison with the outputs of detector memories AM, BM, CM, and DM if this count condition of flip-flop FF-3 corresponds with a traffic actuation having occurred in phase B. If so, further searching will be terminated.

Reference is now made to FIG. 9. Since phase B is traffic actuated, a binary "1" signal is present on input terminal BM' whereupon NOR-gate 220 applies a binary "0" signal to one input of NOR-gate 228. Since a right-of-way signal is being applied to phase A, and not to phase B, then output terminal b of the phase select circuit PS should carry a binary "0" signal. This binary "0" signal is applied to second input of NOR-gate 228. The output terminal "1" of flip-flop FF-3 carries a binary "1" signal which is converted by NOR-gate 212 to a binary "0" signal, which is then applied to a third input of NOR-gate 228. Also, the "0" terminal of flip-flop FF-4 carries a binary "1" signal which is inverted by NOR-gate 216 so as to apply a binary "0" signal to the fourth input of NOR-gate 228. Since all four inputs of NOR-gate 228 carry binary "0" signals, the output of this NOR-gate applies a binary "1" signal through diode 236 to output terminal SS.

Reference is now made to FIG. 6, from which it will be noted that the binary "1" signal at terminal SS is applied to the input of NOR-gate 114 so that this gate applies a binary "0" signal to the input of NOR-gate 116. The output of NOR-gate 116 in turn applies a binary "1" signal to the input of NOR-gate 123 so that the output of this NOR gate now carries a binary "0" signal. Thus, the output of NOR-gate 125 will now carry a binary "1" signal which is applied to clear terminal C of flip-flop FF-3 to prevent further trigger pulses from wave shaper WS from triggering this flip-flop.

Reference is now made to FIG. 2, from which it will be noted that when the select stop terminal SS carries a binary "1" signal, this signal is applied to the second of two inputs of AND-gate 42. Timer circuit T1 had previously timed out and, hence, both inputs of AND-gate 42 carry binary "1" signals, whereupon the AND gate applies a binary "1" signal to one input of NOR-gate 80 in the interval sequencer circuit IS. This causes output circuit g to be deenergized to carry a binary "0" signal and output circuit y to carry a binary "1" signal. As discussed previously with respect to the description of operation of the timer circuits T1 and T2, once the output terminal y becomes energized, the caution timer T2 is actuated so as to time a predetermined period of time as adjusted by the potentiometer 14 in timer control circuit TC-1. Once the timing function has been completed, timer T2 applies a binary "1" signal to input terminal T2' of the phase select circuit.

Reference is now made to FIG. 5, from which it will be noted that once timer T2 has applied a binary "1" signal to input terminal T2', NOR-gate 170 applies a binary "0" signal to one input each of NOR-gates 160, 162, 164, 166, and 168. Since the phase select search circuit completed its searching function after one pulse had been received from wave shaper WS, the output terminal "1" of flip-flop FF-3 now carries a binary "1" signal and the output terminal "0" now carries a binary "0" signal. The condition of the phase next barrier flip-flop FF-4 has not changed, and hence its output terminal "1" still carries a binary "0" signal and its output terminal "0" still carries a binary "1" signal. Since a binary "1" signal is now applied to one of its inputs, NOR-gate 162 applies a binary "0" signal to the input of NOR-gate 180 in flip-flop FF-5. Since both of its inputs carry binary "0" signals, NOR-gate 164 applies a binary "1" signal to the input of NOR-gate 182. Through regenerative action, the output of NOR-gate 182 will now carry a binary "0" signal and the output of NOR-gate 180 will now carry a binary "1" signal. Since one of its inputs carries a binary "1" signal, the output of NOR-gate 168 carries a binary "0" signal which is applied to one input of NOR-gate 186 in flip-flop FF-6. Since both of its inputs carry binary "0" signals, NOR-gate 166 applies a binary "1" signal to the input of NOR-gate 184. Through regenerative action, the output of gate 186 now carries a binary "1" signal, and the output of NOR-gate 184 now carries a binary "0" signal.

When timer T2 completes its timing function it applies a binary "1" signal to the input of NOR-gate 82 in the interval sequencer circuit IS. This causes output circuit y to carry a binary "0" signal and output circuit g to carry a binary "1" signal. Since output circuit g now carries a binary "1" signal, this resets timer memories TM in timer circuits T1 and T2 (FIG. 3) , whereupon the NOR-gates 38 in each of these two circuits carry binary "0" signals. Thus, timer T2 now applies a binary "0" signal to input terminal T2' of the phase select circuit PS.

Referring now to FIG. 5, since a binary "0" signal is now applied to the input of NOR-gate 170, this NOR gate applies a binary "1" signal to one input each of NOR-gates 160, 162, 164, 166, and 168. Accordingly, NOR-gate 160 now applies a binary "0" signal to the phase on logic circuit POL. Since both of its inputs now receive a binary "1" signal, NOR-gate 162 is unchanged and still applies a binary "0" signal to the input of NOR-gate 180. However, since one of its inputs now receives a binary "1" signal, NOR-gate 164 now applies a binary "0" signal to the input of NOR-gate 182. This, however, does not change the status of this flip-flop and NOR-gate 180 and NOR-gate 182 still apply binary "1" and binary "0" signals, respectively, to the phase on logic circuit POL. Since both of its inputs now receive binary "1" signals, NOR-gate 168 is unchanged and still applies a binary "0" signal to NOR-gate 186 in flip-flop FF-6. However, since one of its inputs now receives a binary "1" signal, NOR-gate 166 now applies a binary "0" signal to the input of NOR-gate 184. This, however, does not change the stable state of flip-flop FF-6 and its NOR-gates 184 and 186, respectively, apply binary "0" and binary "1" signals to the input of the phase on logic circuit POL.

Reference is now made to FIG. 8. NOR-gate 190 now receives binary "0" signals from the outputs of NOR-gates 160 and 182. Accordingly, NOR-gate 190 applies a binary "1" signal to the input of NOR-gate 194, which, in turn, applies a binary "0" signal to one input of NOR-gate 208. Since NOR-gate 200 receives a binary "1" signal from NOR-gate 186, NOR-gate 200 applies a binary "0" signal to the second input of NOR-gate 208. Since both of its inputs receive binary "0" signals, NOR-gate 208 applies a binary "1" signal to output circuit b representative that phase b has been selected to be the phase that next receives a right-of-way signal.

NOR-gate 202 receives a binary "1" signal from the output of NOR-gate 198 and, accordingly, output circuit d is deenergized with a binary "0" signal. NOR-gate 204 also receives a binary "1" signal from the output of NOR-gate 198 and, accordingly, output circuit c is deenergized to carry a binary "0" signal. NOR-gate 206 receives a binary "1" signal from NOR-gate 196 and accordingly, output circuit a is now deenergized to carry a binary "0" signal. Since only output circuit b carries a binary "1" signal, the transistor 10 in timer control circuit TC-2 is now actuated into conduction so that go timer T1 now times a predetermined period of time as adjusted by potentiometer 12 in timer control circuit TC-2 to control the time duration of the initial allocation of go time to phase B. As discussed hereinbefore with reference to the operation for phase A, this go signal display will continue unless some other phase is traffic actuated. If so, since a binary "1" signal is applied to terminal T1' upon time out of timer T1, the phase select circuit will commence a searching operation to determine which phase is traffic actuated.

CROSSING THE BARRIER

In the previous description the phase selection operation took place on the same side of the barrier, and hence the phase selection search process terminated when the select stop logic circuit SSL noted that phase B had been traffic actuated and had placed a calling signal. The description which follows will take place on the assumption that the calling phase was phase D and not phase B.

Since it is phase D that is traffic actuated and not phase B, as discussed above, a binary "1" signal is applied to input terminal DM' of the call on other side logic circuit COS (FIG. 7). Thus, NOR-gate 150 applies a binary "0" signal to one input of NOR-gate 152. Output terminal "0" of the phase next barrier flip-flop FF-4 (FIG. 5) carries a binary "1" signal since we are still operating on the left side of the barrier. Thus, NOR-gate 152 applies a binary "1" signal to the input of NOR-gate 122 in the phase select logic circuit PSL (FIG. 6).

Since NOR-gate 122 has received a binary "1" signal, it applies a binary "0" signal to the input of NOR-gate 128. Since timer T1 has timed out, it applies a binary "1" signal to input terminal T1' so that NOR-gate 112 (FIG. 6) applies a binary "0" signal to one input of NOR-gate 114. Since we have not received a select stop signal, the second input of NOR-gate 114 also receives a binary "0" signal. Thus, NOR-gate 114 applies a binary "1" signal to NOR-gate 116 which, in turn, applies a binary "0" signal to one input of NOR-gate 118. The second input of NOR-gate 118 receives a binary "0" signal from the "0" terminal of flip-flop FF-3 which resulted from receipt of the first trigger pulse from the wave shaper WS. Thus, NOR-gate 118 applies a binary "1" signal to the input of NOR-gate 126. Accordingly, both inputs to NOR-gate 128 receive binary "0" signals, whereupon this NOR gate applies a binary "1" signal to the input of NOR-gate 130. NOR-gate 130 in turn applies a binary "0" signal to the clear terminal C of flip-flop FF-4 which permits this flip-flop to be actuated from one stable state to the other by a negative trailing edge of a pulse being applied to its trigger terminal T from output terminal "1" of flip-flop FF-3.

On the next negative trailing edge of a pulse from wave shaper WS, flip-flop FF-3 is changed so that its "1" terminal carries a binary "0" signal and its "0" terminal carries a binary "1" signal. This serves to trigger flip-flop FF-4 from its normal stable state condition during operation on the left side of the barrier to the condition wherein its "1" terminal carries a binary "1" signal and its "0" terminal carries a binary "0" signal.

At this point, the phase select stop logic circuit SSL (FIG. 9) compares the output signals of flip-flops FF-3 and FF-4 along with the signals on output circuits a, b, c, and d against the status of detector memories AM, BM, CM, and DM. If detector memory CM had been actuated due to a phase C detection, the select stop circuit would produce an output signal to prevent further phase select searching operation. However, this is not the case, since only detector memory DM has been so actuated. Accordingly, the searching operation continues; to wit, upon receipt of another pulse from wave shaper WS, flip-flop FF-3 changes its stable state so that output circuit "1" carries a binary "1" signal and output circuit "0" carries a binary "0" signal. Flip-flop FF-4 is not changed by this operation.

Reference is now made to FIG. 9. Since a detector actuation took place in phase D, a binary "1" signal is present on input terminal DM'. Thus, NOR-gate 224 applies a binary "0" signal to one input of NOR-gate 232. Since we are now operating in the right side of the barrier, the "1" output terminal of flip-flop FF-4 carries a binary "1" signal. This is inverted by NOR-gate 214 to apply a binary "0" signal to a second input of NOR-gate 232. Since a binary "1" signal is present on output terminal "1" of flip-flop FF-3, NOR-gate 212 applies a binary "0" signal to a third input of NOR-gate 232. Since we are not yet in the phase D operation, output circuit d of the phase select circuit PS is deenergized and carries a binary "0" signal, which is applied to the fourth input of NOR-gate 232. Since all of its inputs carry binary "0" signals, NOR-gate 232 now applies a binary "1" signal to the select stop output terminal SS.

Referring now to FIG. 2, since timer T1 had timed out, both inputs to AND-gate 42 carry binary "1" signals. Accordingly, AND-gate 42 applies a binary "1" signal to the input of NOR-gate 80 in the interval sequencer circuit IS. This causes output circuit g to be deenergized to carry a binary "0" signal, and output circuit y to carry a binary "1" signal. Accordingly, timer T2 will now commence timing the caution period of time as adjusted by potentiometer 14 in the phase A timer control circuit TC-1. When timer T2 has completed its timing function, it applies a binary "1" signal to input terminal T2' of the phase select circuit (FIG. 5).

Reference is now made to FIG. 5, from which it will be noted that when a binary "1" signal is applied to input terminal T2', NOR-gate 170 applies a binary "0" signal to one input each of NOR-gates 160, 162, 164, 166, and 168. The "1" and "0" terminals of flip-flop FF-3 now respectively carry binary "1" and binary "0" signals. Also, the "1" and "0" terminals of flip-flop FF-4 now respectively carry binary "1" and binary "0" signals. Accordingly, NOR-gate 164 applies a binary "1" signal to the input of NOR-gate 182 in flip-flop FF-5. Thus, through regenerative action, NOR-gate 182 applies a binary "0" signal to the phase on logic circuit and NOR-gate 180 applies a binary "1" signal to the phase on logic circuit POL. Also, NOR-gate 168 applies a binary "1" signal to the input of NOR-gate 186 in flip-flop FF-6. Accordingly, through regenerative action, NOR-gate 184 now applies a binary " 1" signal to the phase on logic circuit POL and NOR-gate 186 applies a binary "0" signal to the phase on logic circuit POL.

As stated hereinbefore, during the description of the same side of barrier operation, after timer T2 completes its timing function, it actuates the inverval sequencer IS so that its output circuit y carries a binary "0" signal and its output circuit g carries a binary "1" signal. This, in turn, causes timer T2 to be reset, whereupon it applies a binary "0" signal to the input of NOR-gate 170 (FIGS. 3 and 5). Accordingly, NOR-gate 160 now applies a binary "0" signal to the phase on logic circuit POL. For the same reasons as discussed with respect to the same side of barrier operation, the outputs of NOR-gates 180, 182, 184, and 186 are not changed from that as discussed above.

Reference is now made to FIG. 8. NOR-gate 198 now receives a binary "1" signal from the output of NOR-gate 184. Accordingly, NOR-gate 198 applies a binary "0" signal to one input of NOR-gate 202. NOR-gate 190 receives a binary "0" signal from NOR-gate 160 and a binary "0" signal from NOR-gate 182. Accordingly, NOR-gate 190 applies a binary "1" signal to the input of NOR-gate 194. NOR-gate 194, in turn, applies a binary "0" signal to the second input of NOR-gate 202. Accordingly, since both of its inputs receive binary "0" signals, NOR-gate 202 applies a binary "1" signal to output circuit d. Since output circuit d now carries a binary "1" signal and binary "0" signals are now carried by output circuits a, b, and c, the transistor 10 in phase D timer control circuit TC-4 is now actuated so that a green signal may be displayed to phase D.

SECOND EMBODIMENT

Reference is now made to FIGS. 10 and 11, which show a second form of traffic controller LC-2. Controller LC-2 like controller LC-1 (FIG. 2) is a four phase, full actuated traffic controller. In the previous description with respect to controller LC-1, this controller was indicated as having a common timing circuit T, four timing control circuits TC-1, TC-2, TC-3, and TC-4, and an interval sequencer circuit IS. Controller L-2, on the other hand, does not include these circuits. Instead, controller LC-2 includes a phase A timer TA, a phase B timer TB, a phase C timer TC, and a phase D timer TD. EAch of these timing circuits take the form, for example, as shown in FIG. 11 with respect to timer circuit TA. However, controller LC-2 like controller LC-1 includes the phase selection circuit PS, which has already been described in detail with reference to FIGS. 5, 6, 7, 8, and 9. Controller LC-2 also includes detector memories AM, BM, CM, and DM associated with detectors DA, DB, DC, and DD. Accordingly, the like components in FIGS. 2 and 10 are identified in FIG. 10 with like character references for purposes of simplifying the discussion of this aspect of the invention.

It will be noted that the select stop terminal SS of the phase select circuit PS is coupled to one input each of timers TA, TB, TC, and TD. Further, each of these timers has an output terminal T1. Terminals T1 are commonly connected through diodes 250, 252, 254, and 256 to input terminal T1' of the phase select circuit PS. Also, each of these timer circuits has an output terminal T2. These output terminals are commonly connected through diodes 258, 260, 262, and 264 to input terminal T2' of the phase select circuit PS. Further, each of the timer circuits TA, TB, TC, and TD has an output terminal y. Output terminals y are commonly connected through diodes 266, 268, 270, and 272 to terminal y' of the phase select circuit PS. Also, the phase timers TA, TB, TC, and TD have output terminals g. Output terminals g and y serve the same function as output terminals g and y of the interval sequencer circuit IS shown in FIG. 2. By making these connections, the phase selection circuit PS will provide phase selection for a four phase, full actuated controller shown in FIG. 10, as well as for the local controller LC-1 described hereinbefore.

Reference is now made to FIG. 11 which is a schematic illustration of phase timer TA. The internal circuitry within phase timers TB, TC, and TD is the same as that of phase timer TA. As shown in FIG. 11, the timer circuit TA includes a green timer circuit 280 and a yellow timer circuit 282. A NOR-gate 300 is coupled to output circuit a of the phase select circuit PS. The output of NOR-gate 300 is applied both to timer circuits 280 and 282. In timer circuit 280, the output of NOR-gate 300 is applied to the input of an NPN-transistor 302 having its emitter connected to ground and its collector connected through a resistor 303 to the B+ voltage supply source. A capacitor 304 is connected across the emitter to collector circuit of transistor 302. The junction of capacitor 304 and resistor 303 is connected to the emitter 308 of a unijunction transistor 306. Transistor 306 has its base B2 connected through a resistor 307 to the B+ voltage supply source and its base B1 connected through a resistor 310 to ground. Also, base B1 is connected to the input of a NOR-gate 312. The output of NOR-gate 312 is connected to the input of a NOR-gate 314. NOR-gates 312 and 314 are connected together to define a bistable multivibrator circuit. A second input to NOR-gate 314 is taken from the output of NOR-gate 300. The output of NOR-gate 314 is connected to output terminal T1 and the output of NOR-gate 312 is connected to one input of an AND-gate 316. The output of AND-gate 316 is connected to output terminal g of phase timer TA. The other input to AND-gate 316 is taken from output circuit a of the phase select circuit PS.

One output of NOR-gate 314 is connected to the input of an AND-gate 318. The second input to AND-gate 318 is taken from the select stop terminal SS of the phase select circuit PS. The output of AND-gate 318 is connected to the input of a NOR-gate 320.

Yellow timer circuit 282 includes an NPN-transistor 322 having its base connected to the output of NOR-gate 320. The emitter of transistor 322 is connected to ground and the collector is connected through a resistor 323 to a B+ voltage supply source. A capacitor 324 is connected across the emitter to collector circuit of transistor 324. Also, the junction of the collector of transistor 322 and capacitor 324 is connected to the emitter 328 of a unijunction transistor 326. This transistor has its base B1 connected through a resistor 330 to ground and its base B2 connected through a resistor 331 to a B+ voltage supply source. Base B1 of transistor 326 is also connected to the input of a NOR-gate 332 having its output connected to the input of a NOR-gate 334. NOR-gates 332 and 334 are connected together to define a two input, bistable multivibrator circuit. A second input to NOR-gate 334 is taken from the output of NOR-gate 300. The output of NOR-gate 334 is connected to output terminal T2. AND-gate 336 has one input taken from the output of AND-gate 318 and a second input taken directly from the output circuit a of the phase select circuit PS. The output of AND-gate 336 is connected to output terminal y.

During the operation of controller LC-2, the phase select circuit PS will, in the fashion as described hereinbefore with reference to FIGS. 5, 6, 7, 8, and 9, select different phase timers for operation. Thus, when output circuit a of phase select circuit PS carries a binary "1" signal, NOR-gate 300 applies a binary "0" signal to the base of transistor 302. This reverse biases transistor 302 and permits capacitor 304 to charge towards the B+ potential. When the voltage level stored by the capacitor exceeds the peak point voltage of the unijunction transistor 306, the capacitor discharges through the emitter 308 to the base B1 terminal and thence through load resistor 310 to ground. This positive potential developed across load resistor 310 serves as a binary "1" signal for application to the input of NOR-gate 312. Thus, the output of NOR-gate 312 applies a binary "0" signal to the input of NOR-gate 314. Since the output of NOR-gate 300 is also a binary "0" signal, both inputs to NOR-gate 314 carry binary "0" signals. Accordingly, NOR-gate 314 applies a binary " 1" signal to output terminal T1 and a binary "1" signal to one input of AND-gate 318. During the period that capacitor 304 is charging to time the green period of time, NOR-gate 312 applies a binary "1" signal to one input of AND-gate 316. The other input to AND-gate 316 is taken from output circuit A of the phase select circuit. Accordingly, AND-gate 316 applies a binary "1" signal to its output circuit g during the period that capacitor 304 is charging.

When the green timer has completed its timing function and applies a binary "1" signal to its output terminal T1, this signal is in turn applied to input terminal T1' of the phase select circuit PS. This causes the phase select circuit to commence its searching operations to determine if another phase is traffic actuated. This operation is the same as has been discussed hereinbefore with reference to FIGS. 5, 6, 7, 8, and 9, and no further description is deemed necessary for a complete understanding of this operation. Once this phase select circuit PS has completed its searching function and has found a calling phase, it applies a binary "1" signal from its select stop output terminal SS to the second input of AND-gate 318 (FIG. 11). Thus, AND-gate 318 applies a binary "1" signal to the input of NOR-gate 320 as well as to one input of AND-gate 336. Since the second input of AND-gate 336 is connected to output circuit a of the phase select circuit PS AND-gate 336 applies a binary "1" signal to its output circuit y. NOR-gate 320 now applies a binary "0" signal to the input of NPN-transistor 322. This reverse biases transistor 322 to permit capacitor 324 to charge toward the B+ potential. When the voltage stored by capacitor 324 exceeds the peak point voltage of unijunction transistor 326, the capacitor discharges through the emitter 328 and base B1 and thence through load resistor 330 to ground. This serves as a positive or binary "1" signal for application to the input of NOR-gate 332. Thus, the output of NOR-gate 334 now carries a binary "1" signal which is applied to output terminal T2 for application to input terminal T2' in the phase select circuit PS. As was described hereinbefore, once a binary "1" signal is applied to input terminal T2' of the phase select circuit PS, the information stored in the phase select search circuit PSS is shifted to flip-flops FF-5 and FF-6 (FIG. 5). It will be recalled from the previous description with reference to FIG. 5, that a second signal in the form of a binary "0" signal was applied to input terminal T2'. The only effect had on that circuit in FIG. 5 is the change of the output of NOR-gate 160 from a binary "1" signal to a binary "0" signal. Accordingly, for the embodiment shown in FIGS. 10 and 11, NOR-gate 160 in FIG. 5 may be short circuited in order to complete the shifting operation. Once the phase select circuit PSS completed its phase selection operation, output circuit A is deenergized to carry a binary "0" signal. Thus, with reference to FIG. 11, NOR-gate 300 applies a binary "1" signal to NOR-gates 314 and 334 to reset the timer circuits 280 and 282, whereupon output terminals T1 and T2 carry binary "0" signals. The remaining aspects of the phase selection operation of phase select circuit PS used in conjunction with a traffic controller of the nature described with reference to FIGS. 10 and 11 is the same as has been described previously with reference to local controller LC-1.

PREEMPTION CONTROL

Reference is now made to FIG. 12 which shows the preemption control circuit. This circuit may be used with the four phase controller shown in FIGS. 10 and 11 and, preferably, with the four phase controller shown in FIG. 2. The preemption control circuit serves the purpose of placing the controller in a particular point in its cycle of operation as dictated by the condition of program switches S1, S2, S3. Whenever a preemption signal occurs, represented by a closure switch SO, the preemption control circuit automatically forces the controller into the programmed operation. This operation is desirable, for example, during a fire lane emergency situation. Another use of the preemption control circuit is when a railroad crosses one of the approaches to an intersection and, hence, upon detection of a train crossing that approach, a preemption control program is placed into effect.

The preemption control circuit serves to control the outputs of flip-flops FF-5 and FF-6 (see FIG. 5) as well as the interval sequencer flip-flop IS (see FIG. 2). As has been described previously with respect to the description of operation regarding phase selection, the output of NOR gate 180 in flip-flop FF-5 serves as the phase on right circuit and is coupled to the input of NOR gate 190 in the phase on logic circuit POL. Similarly, the output of NOR-gate 182 serves as the phase on left circuit and is coupled to the input of NOR-gate 192 in the phase on logic circuit POL. The output of NOR-gate 184 in flip-flop FF-6 serves as the phase on barrier right circuit and is coupled to the input of NOR gate 198 in the phase on logic circuit POL. Similarly, the output of NOR-gate 186 serves as the phase on barrier left circuit and is connected to the input of NOR-gate 200 in the phase on logic circuit POL. The output circuits of NOR-gates 80, 82 in the interval sequencer circuit IS are respectively connected to output circuits g and y. The nature of the binary signals carried by these output circuits determines the status of the controller when operating power is turned on. Thus, if the phase on right output circuit, the phase on barrier right output circuit, and output circuit g each carry binary "1" signals, then phase D is allocated a green signal.

The preemption control circuit includes preemption control switch SO which, as shown in FIG. 12, is represented as a normally open switch. It is to be appreciated, of course, that switches S0, S1, S2, and S3 may take the form of solid state switches, such as transistors. Switch S0, for example, may be a transistor controlled by a remote circuit during a fire lane emergency situation or by a detector for detecting a railroad crossing situation. The preemption control circuit includes NOR-gates 500, 504, 506, 508, 510, and 512. Each of these NOR gates has one input connected through normally open switch S0 to ground as well as through a resistor 514 to the B+ voltage supply source. The outputs of NOR-gates 500, 504, 506, 508, 510, and 512 are respectively coupled to the inputs of NOR-gates 180, 182, 184, 186, 80, and 82. The second input of NOR-gate 500 is coupled through a resistor 516 to a B+ voltage supply source as well as through a normally open program switch S1 to ground. NOR-gate 518 has its input connected to the junction of resistor 516 and switch S1 and its output connected to the second input of NOR-gate 504. NOR-gate 506 has its second input connected through a resistor 520, to a B+ voltage supply source, as well as through normally open program switch S2 to ground. A NOR-gate 522 has its input connected to the junction of switch S2 and resistor 520, and its output connected to the second input of NOR-gate 508. NOR-gate 510 has its second input connected through a resistor 524 to a B+ voltage supply source as well as through normally open program switch S3 to ground. A NOR-gate 526 has its input connected to the junction of switch S3 and resistor 524, and its output connected to the second input of NOR-gate 512.

Program switch S1 serves to control whether the phase on right output circuit or phase on left output circuit will be energized to carry a binary "1" signal. If the switch is closed, then upon closure of switch S0 the phase on left circuit carries a binary "1" signal. If the switch is open, then the phase on right circuit will carry a binary "1" signal, once switch S0 has been closed. Similarly, switch S2 serves when closed to place a binary "1" signal on the phase on barrier left circuit, and when open to provide a binary "0" signal to the phase on barrier right circuit, once switch S0 is closed. Also, switch S3 serves when closed to place a binary "1" signal on output circuit y and when open to place a binary "1" signal on output circuit g, once switch S0 has been closed.

Assume that it is desired that once switch S0 is closed the controller will provide a yellow signal on phase D. If so, then since phase D is on the right side of tHe barrier switch S2 is opened. Also, since phase D is on the right side of the right barrier, switch S1 is opened. However, since we desire to have a yellow signal displayed to phase D, switch S3 is closed. Accordingly, once switch S0 becomes closed, a binary "0" signal is applied to one input of each of the NOR-gates 500, 504, 506, 508, 510, and 512. Since switch S3 is closed, a binary "0" signal is applied to the second input of NOR-gate 510 and to the input of NOR-gate 526. NOR-gate 526, in turn, applies a binary "1" signal to the input of NOR-gate 512. Since one of its inputs carry a binary "1" signal, NOR-gate 512 applies a binary "0" signal to NOR-gate 82. On the other hand, since both of its inputs receive binary "0" signals, NOR-gate 510 applies a binary "1" signal to the input of NOR-gate 80. Through regenerative action, output circuit y of interval sequencer circuit IS carries a binary "1" signal and output circuit g carries a binary "0" signal. Since switch S1 is open, the second input to NOR-gate 500 receives a binary "1" signal and, hence, NOR-gate 500 applies a binary "0" signal to the input of NOR-gate 180. However, both inputs of NOR-gate 504 receive binary "0" signals whereupon this NOR gate applies a binary "1" signal to the input of NOR-gate 182. Through regenerative action, NOR-gate 180 applies a binary "1" signal to the phase on right output circuit and a binary "0" signal to the phase on left output circuit. Since switch S2 is open, one of the inputs to NOR-gate 506 is a binary "1" signal and, accordingly, NOR-gate 506 applies a binary "0" signal to the input of NOR-gate 184. However, both of the inputs of NOR-gate 508 receive binary "0" signals, whereupon NOR-gate 508 applies a binary "1" signal to the input of NOR-gate 186. Through regenerative action, NOR-gate 184 applies a binary "1" signal to the phase on barrier right circuit, and a binary "0" signal to the phase on barrier left circuit. Since binary "1" signals are now carried by the phase on right circuit, the phase on barrier right circuit and output circuit y is indicative of a yellow signal to be allocated to phase D. Accordingly, this program of switches S0, S1, S2, and S3 will force the controller to display a yellow signal to phase D when switch S0 is closed.

ORIENTATION PROGRAMMING CIRCUIT

Reference is now made to FIG. 13 which schematically illustrates the orientation programming circuitry. This circuitry, but for the inclusion of NOR-gate 530 having its input connected to normally open switch S0, is essentially the same as the preemption control circuit described previously with reference to FIG. 12. The output of NOR-gate 530 is connected to one input each of NOR-gates 44, 52, 60, and 70, respectively, located in the detector memories AM, BM, CM, and DM (FIG. 2).

The purpose of this circuitry is that upon each closure of the preemption, or in this case the orientation, switch S0, a binary "0" signal is applied to the input of NOR-gate 530. NOR-gate 530, in turn, applies a binary "1" signal to one input each of NOR-gates 44, 52, 60, and 70. This simulates a traffic detection having taken place in each of the traffic phases A, B, C, and D. One application of this circuit is that when power has failed and has been re-established, each of the phases will sequentially receive traffic signals. In the absence of this feature, when power is returned the controller would display signals in accordance with the positioning of program switches S1, S2, and S3. Since many intersections use spot detectors, as opposed to presence detectors, a traffic detection may not be noted by the controller when power is lost and then returned. Accordingly, a vehicle that had actuated the spot detector and is now awaiting a right-of-way signal must backup to reactuate the spot detector. To prevent this, NOR-gate 530 serves, upon each closure of switch S0, to simulate a traffic detection on all traffic phases. Thus, when power is returned, the controller will cycle once in a sequential fashion to present go traffic signals in phases A, B, C, and D.

Although the invention has been described in connection with preferred embodiments, it will be readily apparent to those skilled in the art that various changes in form and arrangement of parts may be made to suit requirements without departing from the spirit and scope of the invention as defined by the appended claims.

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