A keyboard entry digital data transmission and reception system employing a one-handed keyboard is disclosed. The novel keyboard arrangement and the logic circuitry associated therewith permits single data characters to be rapidly entered by a plurality of sequential key depressions which uniquely define each character.

Current U.S. Class:	178/79 ; 178/17C; 341/34; 400/472; 400/88
Current International Class:	G06F 3/023 (20060101); H03M 11/14 (20060101); H03M 11/16 (20060101); G08b 001/00 (); H04b 001/00 (); H04l 015/02 ()
Field of Search:	178/17C,79,80,81,17.5 340/365,172.5 235/145R

Farmer; Herbert E. Edelberg; Nathan Deeley, Jr.; Harold P.

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Claims

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What is claimed is:

1. Keyboard entry communications apparatus comprising:

keyboard means, said keyboard means having character entry keys fewer in number than the total number of characters comprising the language in which information is to be communicated;

means connected to said keyboard means for encoding signals produced by the operation of each key on said keyboard means;

a plurality of storage devices connected to said encoding means for temporarily storing encoded signals commensurate with key operations;

steering logic means connected to said keyboard means and responsive to each key operation for generating and applying enabling signals sequentially to said temporary storage devices whereby successive key operations will result in an encoded signal being accepted by a different one of said temporary storage devices;

memory means connected to said temporary storage devices and responsive to the enabling of the last storage device in sequence for accepting and storing encoded information from all of said temporary storage devices, said information from all of said temporary storage devices being commensurate with a unique character defined by a plurality of successive key operations;

transmitter means connected to said memory means for transmitting messages stored in said memory means, said messages comprising a plurality of characters each uniquely defined by a plurality of key operations; and

means for selectively enabling said transmitter means.

2. The apparatus of claim 1 wherein said keyboard means includes a space key and wherein said steering logic means is responsive to operation of the space key for generating a signal for simultaneously enabling all of said temporary storage devices whereby an encoded signal commensurate with a space will be applied to said memory means upon operation of the space key.

3. The apparatus of claim 2 further comprising:

display means for providing an intelligible presentation of information entered by said keyboard means on a real time basis, said display means being connected to said memory means and responsive to the entry of encoded information therein for providing an indication of such information.

4. The apparatus of claim 3 wherein said encoding means comprises:

a binary encoder; and wherein said communications apparatus further comprises:

means connected between said temporary storage means and said memory means for converting the plural binary coded signals in said temporary storage devices into a code compatible with said display means.

5. The apparatus of claim 1 further comprising:

means for storing a programmed identification message;

selector means having input terminals connected to said programmed identification message storing means and said memory means, said selector means having an output terminal connected to said transmitter means; and

means responsive to command signals provided by said transmitter means enabling means for controlling said selector means whereby said programmed identification message and keyboard entered message are sequentially delivered to said transmitter means.

6. The apparatus of claim 3 further comprising:

means for storing a programmed identification message;

selector means having input terminals connected to said programmed identification message storing means and said memory means, said selector means having an output terminal connected to said transmitter means; and

means responsive to command signals provided by said transmitter means enabling means for controlling said selector means whereby said programmed identification message and keyboard entered message are sequentially delivered to said transmitter means.

7. The apparatus of claim 4 further comprising:

means for storing a programmed identification message;

selector means having input terminals connected to said programmed identification message storing means and said memory means, said selector means having an output terminal connected to said transmitter means; and

means responsive to command signals provided by said transmitter means enabling means for controlling said selector means whereby said programmed identification message and keyboard entered message are sequentially delivered to said transmitter means.

8. The apparatus of claim 1 wherein said keyboard means comprises:

a one-hand operated key set including ten alpha-numeric information associated keys; and

means for providing a separate electrical output connection commensurate with each key.

9. The key set of claim 8 wherein characters are associated with the keys in alphabetical and numerical order.

10. The apparatus of claim 2 wherein characters defined by certain of said plural sequential key operations will be commensurate with words to be followed by numerical information and wherein said memory means comprises:

a read only memory, said read only memory identifying those words which are to be followed by numerical information and generating a control signal commensurate therewith;

means responsive to control signals provided by said read only memory for providing a signal to said steering logic means which results in all of said temporary storage devices being simultaneously enabled in response to each succeeding key operation until the space key is operated.

11. The apparatus of claim 10 wherein said keyboard means comprises:

a one-hand operated key set; and

means for providing a separate electrical output connection commensurate with each key on said key set.

12. The apparatus of claim 11 wherein said encoding means comprises a binary encoder.

13. The apparatus of claim 12 wherein said memory means further comprises:

means connected between said temporary storage devices and said read only memory for converting plural binary coded signals in said storage devices into a code compatible to presentation to a human operator.

14. The apparatus of claim 13 further comprising:

display means for providing an intelligible presentation of information entered by said keyboard means on a real time basis, said display means being connected to said read only memory means and responsive to the entry of encoded information therein for providing an indication of such information.

15. The apparatus of claim 14 further comprising:

means for storing a programmed identification message;

selector means having input terminals connected to said programmed identification message storing means and said memory means, said selector means having an output terminal connected to said transmitter means; and

means responsive to command signals provided by said transmitter means enabling means for controlling said selector means whereby said programmed identification message and keyboard entered message are sequentially delivered to said transmitter means.

16. The apparatus of claim 1 wherein said encoding means comprises:

a binary encoder.

17. The apparatus of claim 16 wherein said memory means comprises:

means connected to the output terminals of said temporary storage devices for converting plural binary coded signals from said storage devices into a code compatible to presentation to a human subject; and

means connected between said code converter and said transmitter means for storing a complete message in the form of a plurality of characters defined by plural key operations.

18. The apparatus of claim 17 further comprising:

voice synthesizer means adapted to receive messages delivered out of said storing means via said transmitter means in response to operation of said transmitter means enabling means.

19. The apparatus of claim 18 wherein said keyboard means comprises:

a one-hand operated key set including ten alpha-numeric information associated keys; and

means for providing a separate electrical output connection commensurate with each key.

20. The apparatus of claim 19 wherein said keyboard means includes a space key and wherein said steering logic means is responsive to operation of the space key for generating a signal for simultaneously enabling all of said temporary storage devices whereby an encoded signal commensurate with a space will be applied to said code converting means upon operation of the space key.

21. The apparatus of claim 20 further comprising:

display means for providing an intelligible presentation of information entered by said keyboard means on a real time basis, said display means being connected to said code converting means and responsive to the entry of encoded information therein for providing an indication of such information.

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Description

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ORIGIN OF THE INVENTION

The invention described herein was made by employees of the United States Government and may be manufactured and used by or for the Government for governmental purposes without the payment of any royalties thereon or therefor.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the coding and subsequent digital transmission and reception of data and to the presentation of the thus transmitted and received data in readily usable form. More specifically, this invention relates to a keyboard entry data transmission and reception system employing a one-handed keyboard wherein single characters or information bits are uniquely defined by a plurality of sequential key depressions. Accordingly, the general objects of the present invention are to provide novel and improved methods and apparatus of such character.

2. Description of the Prior Art

The necessity of increasing the speed and accuracy of data transmission is particularly evident in the field of air traffic control. At the present time most information exchange between an aircraft and ground controllers is accomplished by voice transmission. The present overload on voice transmission links as utilized for air traffic control is forcing the need for digital message transmission so as to free air time and permit an increase in the number of messages which can be transmitted per unit of time.

In order for digital data link transmission techniques to be acceptable or adaptable for widespread usage, some form of keyboard entry of information is required. The most basic form of keyboard data entry device, of course, comprises the existing standard typewriter keyboard. The standard keyboard typewriter, however, originated as a purely mechanical device. Because of the initial crudity of the mechanical linkages available, the characters on the keys of early typewriters were intentionally positioned in a somewhat awkward arrangement so as to slow the typist to a speed compatible with capabilities of the mechanical apparatus. The original typewriter keyboard layout has persisted to the present time, although substantial equipment improvements have been made, for the very basic reason that a change to a different character layout would require the retraining of millions of typists as well as the rebuilding of all existing typewriters.

Returning to a consideration of the air traffic control problem, with which the present invention is concerned but not limited, space constraints within aircraft cockpits are severe and this factor alone dictates that the means for generating information for the input to a digital message transmission system must be in some form other than a standard typewriter keyboard. As a further factor dictating against the use of a standard typewriter keyboard, obviously an aircraft crewman cannot be expected to have two hands free for efficient operation of a normal QWERTY keyboard.

Special purpose key sets have been developed and are presently in use. The well known Stenotype machine represents one example of one such special purpose keyboard. Extremely high input rates are possible with a Stenotype machine through the use of chord keying. However, use of a Stenotype machine requires an extended period of training and the output is in coded form rather than in normal English text.

To briefly summarize the foregoing, operations within complex man-machine systems are imposing increasing needs for keyboard entry of information under conditions where two-handed keying is not feasible in the face of requirements for the performance of other concurrent tasks. The piloting of airliners, operation of police vehicles equipped with digital communication links and the checkout of complex military and space systems represent examples of technological areas wherein, even in the absence of space constraints, use of a standard typewriter keyboard would be inefficient when keyed by only one hand. Accordingly, a need clearly exists for a simple one-handed keyboard and associated logic systems which may be used for communication purposes. Such equipment, while having initial utility in an area such as air traffic control to replace the present inefficient use of voice transmission, may be applied to a general purpose one-handed typewriter. A typewriter capable of being produced in a pocket-size version would have wide application to students taking lecture notes, or for other persons who must regularly make records, and a similar input device coupled to a speech synthesizer would permit deaf mutes to communicate with the public at large.

SUMMARY OF THE INVENTION

The present invention overcomes the above briefly discussed and other deficiencies and disadvantages of the prior art by providing a limited-key input device having the capability of easy insertion of alphanumeric information. In accordance with the present invention a keyboard data entry device, with keys having electrical contacts which actuate digital logic circuitry, is employed. In the use of a preferred embodiment of the invention, the depression of one key provides an electrical signal which is later modified or added onto by a signal resulting from the depression of a second key; character or bit presentation resulting only after the depression of the second key. The present invention thus comprises a uniquely organized one-handed keyboard, with a limited number of data entry input keys, and associated logic circuitry whereby single characters are uniquely defined by sequential key depressions.

In the disclosed embodiment of the invention, which is directed to an air traffic control application, the keyboard is used to enter a message which is presented on a printer or a volatile display in real time for proofreading; the message comprising a number of two stroke defined characters. The displayed message is simultaneously stored in binary form so that, when proofreading is completed, the message may be transmitted at high speed to a remote terminal where it may, for example, be used to activate a speech synthesizer which then pronounces the message at a normal speaking rate. The digital logic circuitry associated with the one-hand keyboard permits the generation and transmission of normal English text or of mnemonically coded messages. When mnemonically coded messages are transmitted, the logic circuitry recognizes that such a message would normally be followed by digits, for example indicative of altitude or heading, and thus the circuitry performs an automatic shift to numerals until such time as the space key is depressed whereupon the system resumes use of double entered alphabetic characters.

BRIEF DESCRIPTION OF THE DRAWING

The present invention may be better understood and its numerous objects and advantages will become apparent to those skilled in the art by reference to the accompanying drawing wherein like reference numerals refer to like elements in the several figures and in which:

FIG. 1 depicts a representative keyboard layout in accordance with the invention;

FIGS. 2A and 2B, when placed side by side, are an electrical circuit block diagram of data entry, storage and transmission circuitry in accordance with an embodiment of the invention employed in air traffic control; and

FIG. 3 is an electrical circuit block diagram of a receiver which would be employed with the transmission circuitry of FIGS. 2A and 2B.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Solely for purposes of explanation, the present invention will be described in the environment of a data link between an aircraft and a ground controller. As noted above, the invention has much broader utility. With reference to FIG. 1, a basic keyboard layout in accordance with the present invention is depicted. In considering the design of such a limited key set; i.e., a key set having fewer keys than the number of characters which may be printed or words which may be pronounced; it is desirable to place characters on the keys in an easily remembered sequence. Such character placement permits use of a coding scheme which is already familiar to an appreciable proportion of the population of potential users of the apparatus. An additional design consideration is to arrange the key layout in the interest of permitting the full use potential of one hand. In the keyboard of FIG. 1, these design considerations have been fulfilled by arranging the letters and numerals in alphabetical and numerical order, by allocating letters to keys such that the keying of the first two letters of the words in the ICAO phonetic alphabet will uniquely define each letter of the English alphabet and by using a keyboard layout which permits four finger operation.

With the keyboard layout of FIG. 1, since the keys are conveniently placed under the fingers of one hand, rapid keying is possible even though two key strokes are required for each letter to be typed. In the basic form depicted, the keyboard uses only 26 of the possible 100 combinations of two key strokes and there are accordingly 74 additional combinations which may be employed. By way of example, in the English language there are approximately 45 two and three-letter combinations which occur with high frequency and some or all of these combinations can be specified with two-key combinations not used for the phonetic alphabet. Thus, after an operator has learned basic keying of the ICAO combinations, he may be taught the second-order combinations in order to reduce the number of key strokes required to generate a given number of letters. A third level of complexity may, obviously, also be introduced in the interest of utilizing other common combinations of English characters in order to further reduce the number of key strokes required to produce a given amount of text.

The immediately preceding brief discussion is aimed at the generation of normal English text. For special purposes, such as air traffic control, it becomes possible to use other combinations to produce mnemonic coding of special purpose messages. In the preferred embodiment, the combinations required to produce the phonetic alphabet are retained, but the remaining capacity of the keyboard may be filled in a variety of ways. Thus, again considering the example of air traffic control, two-letter mnemonically coded messages may be generated such as:

Char- Ground to Air Air to Ground acter Transmission Transmission ______________________________________ 02 WEather (provides auto- request for WEather matic transmission of information weather information) 05 squaWK identification not used may be followed by a numeric code) 07 You May (permiss- not used ion granted) 10 Contact Wide area not used control (ARTCC) 11 Contact Approach not used control 12 Contact Departure not used control 13 Contact Ground not used control 15 AcKnowledge (ment) AcKnowledge (ment) 19 Contact Tower not used or this may be a request for the frequency if it is not automatically supplied by ground 25 Dump Information Dump Information (means for clearing the display, not a transmitted message, or transfer to another controller) 26 Flight Level? not used in two-character (request for altitude format information) 28 not used Emergency Request for priority in use of voice channel 34 not used may I Go Higher? (request for a higher altitude) 36 not used may I Go Lower? (request for a lower altitude) 46 Hold Level (maintain Holding present Level present altitude) (might be followed by digits to indicate reaching a requested altitude) 49 Hold after Taxiing Holding after Taxiing 51 not used Initial Contact with a new controller. (should automatically provide flight no., aircraft type and other pertinent info.) 52 If Feasible If Feasible 56 I Locate you I Locate the traffic (radar contact) you have pointed out 62 LEave a hold or LEaving (rolling, taking restriction off, departing, etc.) 67 Lost Message Lost Message (request (request for re- for retransmission) transmission) 68 what is your Lowest not used in two-character Speed possible? format 71 you are Now Cleared not used 76 Not Located (can't traffic Not Located find you on radar) 79 not used in two- report of reaching the character format OUter marker 80 Stay With me (remain not used on this frequency) 83 Restriction Gone not used (listed) 90 Thank You Thank You 92 not used in two- estimated Traffic Delay character format requested 99 TUrbulence (possible TUrbulence report from wake of previous aircraft) ______________________________________

With respect to the use of "AK" for acknowledgement, as set forth in the above tabulation, it is to be noted that present voice transmission techniques require that any commands or advisories from the ground be repeated by the pilot to assure the accuracy of reception. For use of the present invention, the symbol "AK" can be employed to cause automatic retransmission and automatic parity check against the original transmission. This, in turn, will permit the ground controller to turn his attention to a second aircraft even before receipt of acknowledgment from the first.

It is also to be noted that a number of the standard messages require subsequent transmission of digits. This may be accomplished through the use of an automatic shift when decoding logic in the transmission circuitry recognizes the particular combinations. The messages which require subsequent transmission of digits include:

Char- Ground to Air Air to Ground acter Transmission Transmission ______________________________________ 17 AltiMeter setting is not used XXXX 26 not used in this format Flight Level is XXX 39 Go To (altitude XXX) Going To (altitude) XXX 41 Hold at Altitude XXX Holding Altitude XXX 44 Hold Heading XXX holding Heading XXX 48 Hold Speed at XXX Holding Speed at XXX 58 Increase Speed to XXX Increasing Speed to XXX 68 not used in this format Lowest Speed possible is XXX 69 Locate Traffic at XXX not used in this format 79 OUter marker is XXX not used in this format 82 Slow Down to XXX knots Slowing Down to XXX knots 86 Report at Level (alt) Reporting at Level XXX XXX 92 Traffic Delay estimate not used in this format is XXX 96 Turn Left to Turning Left to XXX XXX heading heading 98 Turn Right to Turning Right to XXX XXX heading heading ______________________________________

Without going into detail herein, it is further to be noted that the inclusion of specific alpha capabilities permits modification of standard messages and also emergency messages such as might be required should the pilot be forced to undertake a collision avoidance course change. Also, because the messages are so short, rather than employ a back space key, when an entry error is made the entire message may be eliminated by depressing a cancel key. Since all of the standard messages as noted above start with alphas, but may end with numerics, a dash or space key is provided to permit the generation of multiple message units. In the embodiment being described, the space key serves as an automatic shift key to return the alphas for the start of the next message unit.

Referring now to FIGS. 2 and 3, circuitry in accordance with an embodiment of the invention intended for use in an air traffic control environment is shown in block diagram form. The circuitry of FIGS. 2 and 3 illustrates the principals of double keying and the logic required to implement this keying technique. In FIG. 2 a keyboard 10, which may be arranged in the same manner as the keyboard of FIG. 1, is used to enter a message in the logic circuitry. The entered message is presented on a printer or a volatile display 12 in real time for proofreading and is simultaneously stored in binary form in a storage device 14 so that, when proofreading is completed, the message may be transmitted at high speed to a remote terminal. The transmission may, of course, be by radio waves and an exemplary remote terminal is depicted in FIG. 3. The received message may be used to activate a speech synthesizer 16 in the remote terminal which then pronounces the message at a normal speaking rate.

In the operation of the embodiment of FIGS. 2 and 3, the first key-press is encoded into binary form in a twelve line to binary encoder 18. The encoded signal commensurate with the first key-press is thereafter stored in a first four bit latch 20. The second key stroke is encoded by encoder 18 and stored in a second four bit latch 22. The eight bits of data thus generated and stored in latches 20 and 22 are presented to a read only memory 24 which adjusts the dual binary code to a code compatible with the display device 12 and voice synthesizer 16. The words or characters are stored and displayed on a real time basis for proofreading before transmission, under the control of display storage and control circuit 26, and are simultaneously stored in a first-in first-out (FIFO) register which comprises storage device 14. Each entry into FIFO register 14 increments a counter 28 which counts the number of entries. The counter 28 will be counted down to zero as data are taken out of FIFO register 14 for transmission. When a complete message is entered, a transmission button located remotely of the keyboard 10 is pressed thereby generating a signal which clears the display, if display device 12 is a volatile display rather than a hard copy printer, and turns on a parallel-to-serial converter 30 and associated transmitter 32. The "transmit" signal also initiates the operation of a further counter 34 which controls a pre-programmed identification message read only memory 36. Counter 34 is incremented with each word transmitted until the complete identification message is transmitted. An AND/OR logic selector array 38 then selects the output of FIFO register 14 and delivers the keyboard-entered message from storage device 14 to converter 30 for transmission. Each word transmitted decrements the word counter 28 until it reaches zero, commensurate with complete message transmitted, at which time the counter 28 causes the generation of a control signal which results in converter 30 and transmitter 32 being turned off and the system readied for the next data entry.

The above briefly described entry, storage and transmission circuitry will now be described in greater detail. Before using the system, a "clear" button 38 is depressed to generate a signal which, under the command of steering logic 40, initializes the system. The "clear" switch 38 will typically be located remotely of the keyboard and the signal generated thereby will result in the following functions being accomplished:

1. Clear the display storage and control circuit 26 thus also clearing display 12;

2. Clear the FIFO register 14 thereby also clearing the parallel-to-serial converter 30;

3. Reset the up/down message word counter 28 to zero thereby also setting the output of a zero detector 42 to zero;

4. Reset the "message present" register 44 to the "message not present" state;

5. Reset a transmit register 46 to the "not transmit" state;

6. Reset a "number next" register 48 to the "no number next" state; and

7. Reset the steering logic 40 to accept the first key stroke of a two-key stroke input character.

8. Reset the preprogrammed message word counter 34 to zero.

To enter a two-key stroke character, which will typically correspond to a spoken word from the voice synthesizer 16 of FIG. 3, any one of the 12 keyboard keys other than the space key is depressed. The 12 lines of data from keyboard 10 are encoded by the 12 line-to-binary encoder 18 and presented at the inputs of the two four-bit latches 20 and 22. The 12 line to binary encoder 18 may, for example, comprise a plurality of RCA type CD4002A and CD4011A logic gates interconnected to assign a unique binary code to each input line while the four-bit latches 20 and 22 may comprise RCA type CD4042A quad latches.

When the first key is depressed a key press detector circuit 50 provides an input signal to steering logic 40 via a delay circuit 52. The purpose of the delay imparted by circuit 52 is to allow the encoded information to settle at the inputs of the latches 20 and 22 prior to the appropriate latch or latches being clocked by an output signal provided by steering logic 40. The clock signal provided by steering logic 40 will cause the four-bit signal commensurate with the first key depressed to be temporarily stored in latch 20. The key press detector 50 may also be an RCA type CD4002A and CD4011A logic gate array arranged as an "OR" function of the 12 key lines and the delay circuit 52 may comprise an RCA type CD4013 flip-flop circuit or equivalent. The steering logic 40, which provides alternate clocking signals for latches 20 and 22, may comprise an RCA type CD4013A flip-flop, RCA type CD4011A and type CD4001A gates and RCA type CD4009A inverters interconnected to give the following performance. The "clear" signal from switch 38 will set the flip-flop, which is connected in a toggle mode, whereby the flip-flop is ready to receive the first key stroke. A subsequent signal from delay circuit 52 toggles the flip-flop and thus sends a positive voltage level change to latch 20. Another signal from delay 52 toggles the flip-flop thereby sending the positive signal to latch 22. The next signal from delay 52 will cause, in the same manner, the signaling of latch 20 again. This action continues as two-keystroke characters are entered. If the space key is depressed, both latches are signaled when delay 52 causes the flip-flop to be toggled thereby entering a space. The space key generated signal also sets the flip-flop to be ready for a subsequent "first" key stroke. Similarly, a logic "high," indicative of "number next," from register 48 will enable both latches to be signaled when delay 52 signals the flip-flop.

The system remains in the above described state until a second key depression is sensed. The second key stroke is encoded in the same manner as the first and is presented to the inputs of latches 20 and 22. The second key stroke is also detected by the key press detector 50 which, after the delay imparted by delay circuit 52 in the interest of allowing the data to settle at the inputs of the latches, signals the steering logic 40 which clocks latch 22 and stores the second key stroke therein. At this stage, the two latches 20 and 22 hold eight bits of data which are uniquely defined by the two key strokes and these eight bits are individually presented to the input of the read-only memory input converter 24. The read-only memory code converter 24, which may comprise a plurality of Intel type 1702 programmable read-only memories, transforms the unique input data into a unique coded word address which is recognized and used by the voice synthesizer and the real time display 12.

The signal which strobes or clocks latch 22 after the second key stroke also, after a delay imparted by circuit 54, clocks the FIFO storage register 14, the display storage and control circuit 26 and the up/down message word counter 28. The delay circuit 54, which may comprise an RCA type CD4013A flip-flop, imparts a time delay which allows the output data from code converter 24 to settle at the inputs to the FIFO storage register 14 before being clocked into the storage register. The FIFO storage register 14 may, for example, comprise a plurality of Fairchild type 3341 storage registers while the up/down message counter 28 may comprise a series of cascaded RCA type CD4029A counters. The display storage and control circuit 26 will be commensurate with display 12 and the two units will typically be acquired as a single commercially available display unit.

After being clocked by the delayed latch 22 strobing pulse, FIFO storage register 14 will have the first eight-bit word stored in its first storage location. The display storage and control circuit 26 also stores the first eight-bit word and displays the symbol or word on the display 12. The up/down message word counter 28 increments each time a word is entered into the FIFO storage register 14. A zero detector 42 connected to counter 28 changes state when the up/down counter 28 is clocked. Zero detector 42 may, for example, comprise a series of RCA type CD4002A and CD4011A gates connected to perform a "NOR" function whereby detector 42 will provide a "high" output when the binary output of counter 28 is zero and a "low" output at all other times.

Subsequent to completion of the operations described above, the steering logic 40 is now ready for the first key press of another two-keypress entry. If the next key press is a space key, the steering logic is signaled directly via conductor 39 and both of latches 20 and 22 are strobed thereby storing the binary representation of the space key in both latches. The logic then proceeds as if two keys had been sequentially depressed and stores a space code in the FIFO storage register 14 and the display storage and control circuit 26; display device 12 thus displaying a space.

After depression of the space key, the steering logic is again ready for the first key stroke of a two key stroke pair. If the two key strokes of a pair define a word which in the specialized usage indicated above is always followed by a number, this fact will be detected by read-only memory 24 as a consequence of its programming. Read-only memory 24 will, accordingly, recognize the combinations which are to always be followed by numbers and will generate a signal commensurate with this information for application as the data input to a "number next" register 48. The "number next" register 48 has applied, as control inputs thereto, a signal generated by depression of the space key and the doubly delayed output commensurate with the strobing of latch 22; the second delay being imparted by delay circuit 58 which may comprise an RCA type CD4013A flip-flop. The "number next" register 48 may comprise merely an RCA type CD4013A flip-flop circuit which is sampled by the doubly delayed strobe pulse from the delay circuit 58. When sampled, register 48 transfers the data input from converter 24 to its output terminal thereby signaling the steering logic that the next key presses are to be treated as space key presses and stored in both latches. The information transferred from the input to the output of "next number" register 48 is also fed back to the input of code converter 24 and signals the code converter that the eight lines of input information generated by the strobing of both of latches 20 and 22 is not a normal double key press but rather a number whose value is determined by the redundant information contained in both of latches 20 and 22. The delay imparted by circuit 58 will be sufficiently long to insure that the input address of code converter 24 does not change until the eight-bit word from the code converter read-only memory has been stored in both FIFO storage register 14 and display storage and control circuit 26.

Each key stroke after an entry which is determined as having "numbers follow it" by the code converter-read only memory 24 is stored in the above described manner after a single key press until such time as the space key is pressed. The depression of the space key, in the manner described above, enters a space into FIFO storage register 14 and display storage and control 26 and resets the "number next" register 48. This action, in turn, returns the steering logic 40 to its normal routine of entering two key strokes.

The above described process of entering information continues, each character incrementing the up/down message word counter 28 as a word is entered into the storage register 14, until the complete message has been entered. After the complete message has been entered, the operator proofreads the message on display 12 and transmit it by depressing the transmit button 60. The momentary closing of the transmit switch 60 sets the "message present" register 44 to the "message present" state and sets a message control register 62 to the "preprogrammed message" state. The setting of message control register 62 signals the AND/OR select network 38 to gate a preprogrammed message to the transmitter in the manner to be described below. The message present register 44 and message control register 62 may each comprise an RCA type CD4013A flip-flop circuit. The AND/OR selector network 38 may comprise a pair of RCA CD4019A gates and a CD4009A inverter connected so as to transfer either the eight lines of data from register 14 or the eight lines of data from ROM 36 to the parallel-to-serial converter 30 depending on the logic state of the data select line from message control register 62.

The state of message control register 62, in addition to being applied as a control input to AND/OR selector network 38, is delivered as an input to a clock distributor 64. The clock distributor 64, which may comprise an array of RCA type CD4011A gates, type CD4009A inverters and an RC differentiator circuit. Distributor 64, upon receipt of a signal from register 62 commensurate with "transmit signal being received," provides a "clock out" signal to register 14. This "clock out" signal causes the first character entered from the keyboard to be transferred to the output of register 14. The output of distributor 64, by application to counter 34, also enables further signals from converter 30 to pass through a counter 34. However, after a further signal from register 62, indicative of "preprogrammed message transmission completed," the signals from converter 30 are passed to register 14 to "clock out" the register and to count message counter 28, rather than counter 34, down until the complete message is transmitted. To describe the operation in more detail, clock distributor 64 generates signals for clocking the preprogrammed identification word counter 34 and for resetting message counter 28 to zero. However, clock distributor 64 does not provide output signals until being enabled by an output from the parallel-to-serial output converter 30. The transmit signal generated by the closing of switch 60 is delayed, by means of a delay circuit 66, to insure that the message present register 44 and the message control register 62 are set correctly and the transmit signal is thereafter employed to activate the transmit register 46. The activation or setting of transmit register 46 enables the parallel-to-serial converter 30 which, in turn, gates clock distributor 64 thereby permitting the clock distributor to send one clock pulse to the preprogrammed identification message word counter 34. The clock pulse applied to counter 34 from distributor 64 allows the preprogrammed identification word counter to count to binary one and the output of counter 34 is presented at the address input of the preprogrammed identification message read only memory 36.

Read only memory 36 is programmed with a unique identification message, for example an aircraft flight number and other identifying information, in the form of a series of words stored in such a manner that the words to be transmitted sequentially are stored with addresses in a binary count mode. Thus, the first identification word has binary address number one, the second word has binary address number two, etc. through address word N which is the last word in a preprogrammed identification message which has binary address N. To briefly describe the transmission of the identification message, the read only memory 36 will present identification message word number one through the AND/OR select gate array 38 to the transmitter 32 via the parallel-to-serial converter 30 and a MODEM (modulator/demodulator) which will be associated with transmitter 32. When the transmitter is ready to transmit the next word, the parallel-to-serial converter 30 signals clock distributor 64 which sends a second clock pulse to message counter 34. The message counter thereupon addresses identification message word number two in read only memory 36 and causes this word to be presented to the transmitter in the above described manner. This mode of operation will continue until identification message word number N + 1 is addressed in read only memory 36 by counter 34. The address commensurate with identification message word N + 1 is recognized by an "end of preprogrammed message" detector 68 which signals message control register 62 that the identification message has been transmitted. The message control register 62 is thereupon reset and, in turn, gates clock distributor 64. This action causes the clocking pulses generated by distributor 64 to be switched from the input to counter 34 to the clock down and clock out inputs respectively of up/down counter 28 and FIFO storage register 14. The switching control signal from message control register 62 is, in addition to application to clock distributor 64, applied to the data select input of AND/OR selector network 38 and causes network 38 to switch the output of storage register 14 to the transmitter. The first eight-bit keyboard character is now presented to the MODEM in the transmitter 32 via the parallel-to-serial converter 30. The converter 30, when the transmitter has completed the transmission of the first eight-bit word, will signal clock distributor 64 which sends a further clock pulse to up/down counter 28 and register 14. The up/down counter is decremented one binary count and the second keyboard entered eight-bit word is presented to the transmitter. This sequential indexing and transmission of the keyboard entered message continues until the last word of the message has been transmitted as indicated by up/down counter 28 reaching zero. The zero state of counter 28 is detected by zero detector 42 which again changes state thereby resetting the "message present" register 44 to the "message not present" state. The resetting of register 44, in turn, causes the transmit register 46 to be reset to the "not transmit" state thereby turning off transmitter 32.

In one embodiment of the invention the identification word counter 34 comprises an RCA type CD4024A binary counter and the programmed identification message read only memory 36 is an Intel type 1702 programmable ROM. The end of preprogrammed message detector 68 comprises an array of RCA type CD4002A gates, type CD4011A gates and type CD4009A inverters interconnected to give a "high" output to the message control register 62 when counter 34 contains the address of preprogrammed identification message word N + 1, and a "low" output at all other times. The parallel to serial converter 30 and transmitter 32 comprises a Motorola Model No. MC2257L transmitter used in association with any commercially available MODEM. The delay circuit 66 is identical to delay circuit 54 and the transmit register 46 comprises merely an RCA type CD4013A flip-flop circuit.

Upon completion of the message entry and transmission cycle, as described above, the system must be made ready for another cycle. This may be accomplished by depressing a "clear all" key 70 or, alternatively, the "transmitter-off" signal from transmit register 46 may be utilized to clear the system; for example in the same manner as shown with respect to the display storage and control circuit 26.

Referring now to FIG. 3, the message receiver system comprises a receiver 80 which includes a serial-to-parallel converter. Receiver 80 may, for example, comprise a Motorola Model No. MC2254L terminal receiver. The received message is translated from serial-to-parallel format and eight lines of data are presented by receiver 80 to the input of a first in first out (FIFO) register 82. As each word is entered into FIFO register 82, an up/down counter 84 is clocked up one binary count. Subsequent to the clocking of counter 84, the voice synthesizer 16 is triggered and, as it finishes a word, the "finished" pulse will be employed to count down counter 84. The "finished" pulse from synthesizer 16 also, through a delay, causes retriggering of the synthesizer. This action continues until the up/down counter 84 returns to the zero state commensurate with the message being completely read-out of FIFO storage register 82 at which time the synthesizer trigger pulses are terminated.

To describe the receiver system in more detail, the operation of the receiver starts with a transmitted message activating receiver 80 which takes the incoming eight-bit serial words and converts them to eight-bit parallel words. Receiver 80 also generates a "character ready" pulse when a complete character has been received. The eight-bit parallel words from receiver 80 are presented to the input of FIFO register 82 which may comprise a plurality of Fairchild Model 3341 storage registers. The "character ready" pulses are applied to the "clock in" input to register 82 and cause the storage register to store the eight-bit words in sequential storage locations. The "character ready" pulse is also employed to clock up the up/down word counter 84, which may comprise an RCA type CD4029A binary counter, each time a character is ready and entered into register 82. The first "character ready" pulse commensurate with a transmitted message is also employed to turn on a message present register 86. The message present register may comprise merely an RCA type CD4013A flip-flop circuit. A signal commensurate with the setting of message present register 86 is capacitively coupled, via a delay circuit 88 which imparts sufficient delay to allow the first few words transmitted to settle in storage register 82, to the "clock out" input of register 82 via OR gate 96. The clocking of register 82 presents the first character entered into the first in-first out storage register at the input of the voice synthesizer 16. Delay circuit 88 may comprise merely an RCA type CD4013A flip-flop circuit. The delayed signal commensurate with the setting of message present register 86 is also applied to an "enable" gating circuit 90. Gating circuit 90 may comprise an array of RCA type CD4011A gates, a type CD4009A inverter and an RC differentiator circuit. When the data line from delay 88 goes "high," gating circuit 90 sends a pulse to synthesizer 16 and counter 84. During the time the input to gating circuit 90 is "high," signals coming from delay 94 are passed through circuit 90 to synthesizer 16 and counter 84. When the input from delay 88 is returned to a "low" state, gating circuit 90 blocks the signal from delay 94. Thus, the "start" command from gating circuit 90 allows synthesizer 16 to speak one word determined by the eight-bits of input information. The start command also clocks down one binary count from up/down counter 84 each time it activates the voice synthesizer. The word is, of course, generated by means of a speaker 92 associated with synthesizer 16. The voice synthesizer may be a commercially available device presently available from McDonnel-Douglas Electronics Corporation and other sources.

Upon completion of each word the voice synthesizer generates a "ready next word" signal which is applied to FIFO storage register 82 via OR gate 96, and also to a delay circuit 94. The "ready next word" signal thus causes storage register 82 to present the next word that has been entered therein in sequence to the voice synthesizer input. The delay circuit 94, which may be identical to delay circuit 88, provides time for the data from storage register 82 to settle at the voice synthesizer input before permitting the synthesizer to retrigger itself via gating circuit 90. This action will continue with data loaded into the FIFO storage register 82 from receiver 80 being taken out of the storage register by the voice synthesizer until the up/down counter 84 reaches zero. The counter 84 will reach zero when the complete message has been generated by the voice synthesizer because the synthesizer has a much slower data rate than the transmitter and receiver. A zero detector 92, which may comprise an array of RCA type CD4002A and CD4011A logic gates interconnected to perform a "NOR" function. Zero detector 92 senses the condition of zero count in up/down word counter 84 and generates a control signal for the message present register 86. That is, detector 92 provides a logic "high" output to message present register 86 when the output of counter 84 is a binary zero and provides a logic "low" at all other times. The message present register 86 thereupon, via the delay 88, interrupts the next "word ready" signal from the voice synthesizer by resetting gating circuit 90 and thus stops the self-triggering of the voice synthesizer. Accordingly, the sound generation is terminated and the system remains ready to receive the next transmitted message. Voice synthesizer 16 may, of course, be replaced by or parallelled with a visual and/or hard copy display device.

The embodiment of the invention described above is a rather complex system specifically intended for use in an air traffic control environment. It will be obvious to those skilled in the art that various modifications and substitutions may be made, without the exercise of invention, in the interest of utilizing the invention in less demanding environments. Accordingly, it is to be understood that the present invention has been described by way of illustration and not limitation.

It should also be obvious that by the use of a minor change in the ICAO phonetic alphabet involving the substitution of such words as "George," "Isaac," "Larry" and "Zebra," respectively, for "Golf," "India," "Lima" and "Zulu," sequential keying of the first two letters of the words of this revised vocabulary on the existing Bell Touchtone Keyboard yields combinations which uniquely define the desired letters. This permits the use of telephone lines for the transmission of hard copy or for computer interrogation with no requirement for special equipment at the originating end of the system.

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