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United States Patent | 5,134,585 |
Murakami , et al. | July 28, 1992 |
A circuit for repairing a defective memory cell is provided between a row or column decoder and a memory cell array. When the decoder has n output lines, the memory cell array includes at least (N+1) row or column lines, where n is an integer. The repair circuit includes connection circuit for connecting the output lines of the decoder to the row or column lines, and a circuit for defining the connection of the connection circuit. The connection circuit includes n switching elements each of which is operable to connect one output line of the decoder to at least two row or column lines. The defining circuit defines the connection path of each switching element such that the output lines of the decoder is connected in one to one correspondence to successively located row or column lines excluding a row or column line connecting a defective memory cell. The defining circuit includes a series of laser programmable fuse elements provided between an operation voltage supply and a ground line. The repair circuit occupies a reduced area of a chip because of no spare decoder and no program circuit and it carries out a reliable and fast memory repair because of the reduced number of the fuse elements to be blown off.
Inventors: | Murakami; Shuji (Hyogo, JP), Wada; Tomohisa (Hyogo, JP), Anami; Kenji (Hyogo, JP) |
Assignee: |
Mitsubishi Denki Kabushiki Kaisha
(Tokyo,
JP)
|
Appl. No.: | 07/500,965 |
Filed: | March 29, 1990 |
Jun 05, 1989 [JP] | 1-142450 | |||
Current U.S. Class: | 365/200 ; 714/5.1; 714/711 |
Current International Class: | G11C 29/00 (20060101); G11C 007/00 (); G11C 029/00 () |
Field of Search: | 365/200,201,189.01 371/10.1,10.2,10.3 |
4389715 | June 1983 | Eaton, Jr. et al. |
4691301 | September 1987 | Anderson |
4703436 | October 1987 | Varshney |
4707810 | November 1987 | Ferrant |
4761767 | August 1988 | Ferrant |
4791319 | December 1988 | Tagami et al. |
4967394 | October 1990 | Minagawa et al. |
61-61300 | Mar., 1986 | JP | |||
61-35636 | Aug., 1986 | JP | |||
K Ochii et al, "An Ultralow Power 8K.times.8-Bit Full CMOS RAM with a Six-Transistor Cell", IEEE Journal of Solid-State Circuits, vol. SC-17, No. 5, Oct. 1982, pp. 798-803. . R. J. Smith et al, "32K and 16K Statis MOS RAMS using Laser Redundancy Techniques" IEEEE ISSCC 1982, Feb. 1982, pp. 252-253.. |