United States Patent: 3664116

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United States Patent	3,664,116
Emerson , et al.	May 23, 1972

DIGITAL CLOCK CONTROLLED BY VOLTAGE LEVEL OF CLOCK REFERENCE SIGNAL

Abstract

A digital clock circuit particularly suited for monolithic integration wherein the counting rate of the clock is variable from a normal to a faster rate in response to the level of a 60 Hz voltage derived from the power line and applied to a single input terminal as a clock reference signal.

Inventors:	Emerson; Paul Gene (Liverpool, NY), Thamhain; Hans Jurgen (Liverpool, NY), McIntosh; Bruce Cromwell (Utica, NY)
Assignee:	General Electric Company (
Appl. No.:	05/025,930
Filed:	April 6, 1970

Current U.S. Class: 368/87 ; 368/187; 368/200; 968/891; 968/910; 968/961; 968/972

Current International Class: G04G 13/00 (20060101); G04G 13/02 (20060101); G04G 9/00 (20060101); G04G 19/06 (20060101); G04G 9/10 (20060101); G04G 5/00 (20060101); G04G 19/00 (20060101); G04G 5/02 (20060101); G04c 003/00 (); G04c 021/04 (); G04b 019/30 ()

Field of Search: 58/23,50,38,23A

Foreign Patent Documents


791,946	Aug., 1968	CA

Primary Examiner: Tomsky; Stephen J.
Assistant Examiner: Simmons; Edith C.

Claims

What is claimed and desired to be secured by Letters Patent of the United States is:

1. A digital clock comprising:

a. counting means;

b. means for generating a reference signal at a first repetition rate;

c. conversion means responsive to said reference signal for producing a signal at a second repetition rate; and

d. control means responsive to the voltage level of said reference signal for selectively applying signals at said first or second repetition rates to said counting means to control the counting rate thereof.

2. A digital clock comprising:

a. counting means;

b. means for generating a reference signal at a first repetition rate and at first, second or third voltage levels;

c. conversion means responsive to said reference signal for producing signals at second and third repetition rates; and

d. control means selectively responsive to said first, second or third voltage levels of said reference signal to respectively apply signals at said first, second or third repetition rates to said counting means to control the counting rate thereof.

3. The digital clock defined in claim 2 wherein the application of signals to said counting means at said first, second and third repetition rates respectively defines fast set, slow set and normal counting rates thereof.

4. The digital clock defined in claim 2 wherein said first repetition rate is 60 Hz, said second repetition rate is 2 per second and said third repetition rate is 1 per minute.

5. The digital clock defined in claim 2 wherein said counting means includes a clock counter and an alarm counter.

6. The digital clock defined in claim 5 wherein said control means includes gating means selectively channelling signals at said first, second or third repetition rates to said clock counter and said alarm counter.

7. The digital clock defined in claim 6 including comparator means responsive to said clock counter and said alarm counter to provide an indication when the counts of said clock counter and said alarm counters are the same.

8. The digital clock defined in claim 6 including display means responsive to said clock and alarm counters to provide a display of the counts thereof.

9. The digital clock defined in claim 8 wherein said display means is responsive to said gating means to selectively display the counts of said clock or alarm counters.

10. The digital clock defined in claim 2 wherein said control means includes:

a. first and second voltage dividers having said reference signal applied thereto;

b. means responsive to the voltage level at an intermediate point of said first voltage divider to apply a signal at said first repetition rate to said counting means; and

c. means responsive to the voltage level at an intermediate point of said second voltage divider to apply a signal at said second repetition rate to said counting means.

11. The digital clock defined in claim 10 wherein:

a. said first voltage divider comprises first, second and third serially connected field effect transistors and said intermediate point of said first voltage divider is the junction between said second and third transistors; and

b. said second voltage divider comprises fourth and fifth serially connected field effect transistors and said intermediate point of said second voltage divider is the junction between said fourth and fifth transistors.

12. A counter comprising:

a. a counting stage;

b. conversion means responsive to a reference signal at a first repetition rate for producing a signal at a second repetition rate; and

c. control means responsive to the voltage level of said reference signal for selectively applying signals at said first or second repetition rates to said counting stage to control the counting rate thereof.

13. A digital clock comprising:

a. clock counting means,

b. alarm counting means,

c. means for generating a reference signal,

d. control means responsive to said reference signal for selectively establishing the count of said clock counting means and alarm counting means,

e. display means responsive to said clock and alarm counting means for providing a display of the counts thereof, and

f. said control means including means for displaying the count in said alarm counting means without interferring with the normal counting operation of said clock counting means.

14. A digital clock as defined in claim 13 wherein said reference signal is at a first repetition rate, which further includes conversion means responsive to said reference signal for producing signals at second and third repetition rates and wherein said control means is responsive to said reference signal for selectively applying signals at said first, second or third repetition rates to said clock counting means and for selectively applying signals at said second or third repetition rates to said alarm counting means.

15. A digital clock as defined in claim 14 which includes means for providing first, second or third voltage levels for said reference signal and wherein said control means is selectively responsive to said first, second or third voltage levels.

Description

BACKGROUND OF THE INVENTION

The familiar rotating hand clock has been used for hundreds of years to provide a time of day display. While the suitability of this familiar display is rarely questioned, it appears upon consideration that such a display does not provide the type of data most readily assimilated by the human brain. Indeed, one who has observed the struggles of a child learning to tell time can appreciate that telling time from a rotating hand clock is a relatively sophisticated and multistep operation involving a good deal of interpolation.

Other more easily assimilated time of day displays have also been available. Thus both mechanical and electronic digital clocks providing a digital display of hours and minutes have found limited use.

However, such digital clocks have heretofore been generally complex and expensive and accordingly ill suited for consumer use.

Indeed, heretofore only mechanical digital clocks which are relatively noisy, unreliable and difficult to set have been available to the consumer.

Thus, there is a real need for an inexpensive, easy to set electronic digital clock suited for consumer use. Such a clock should be small in size to insure design flexibility and be capable of providing an alarm at a preset time.

These needs are satisfied by the electronic digital clock circuit of the invention which is particularly suited for monolithic integration.

Accordingly, it is an object of the invention to provide an inexpensive electronic digital clock suitable for consumer use.

It is a further object of the invention to provide an electronic digital clock that is easily set by the user.

It is yet another object of the invention to provide an electronic digital clock including an alarm indication at a preset time.

It is still another object of the invention to provide an electronic digital clock particularly suited for monolithic integration.

SUMMARY

These and other objects are achieved in one embodiment of the invention by the provision of a digital clock circuit wherein easy setting is achieved through use of a counting rate control circuit whereby the counting rate is variable between normal, slow set and fast set rates in response to the level of the 60 Hz line voltage applied to a single input terminal as a clock reference signal.

BRIEF DESCRIPTION OF THE DRAWINGS

The novel and distinctive features of the invention are set forth in the appended claims, the invention itself along with further objects and advantages thereof may be best understood by reference to the following description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a generalized block diagram of the electronic digital clock of the invention;

FIG. 2 is a logical diagram of the counting rate control circuit of the invention as depicted in block diagram form in FIG. 1;

FIG. 3 is a logical diagram of the gating circuit shown in FIG. 1;

FIG. 4 is a wave form diagram describing the operation of the counting rate control circuit of FIG. 2; and

FIG. 5 is a schematic diagram of a preferred input-output circuit for the electronic digital clock depicted in FIG. 1.

DETAILED DESCRIPTION OF AN ILLUSTRATIVE EMBODIMENT

Referring to FIG. 1, there is shown a generalized block diagram of the digital clock of the invention. As depicted, a clock reference signal in the form of the readily available 60 Hz line voltage is applied via line 1 to a rate control circuit 3. The rate control circuit 3, the logical diagram of which is shown in detail in FIG. 2, provides shaped 60 Hz output pulses on line 5, such pulses being applied to a divider 7 which produces a single pulse output for every 30 input pulses thereby providing a 2 pulse per second output on the line 9. Line 9 is connected to a second divider 11 which provides a single pulse output on the line 13 for every 120 pulses appearing on line 9, a 1 pulse per minute output accordingly appearing on line 13 and being applied to a gating circuit 15.

In accordance with the invention, the rate control circuit 3 is responsive to the voltage level of the 60 Hz clock reference signal at line 1 in order to selectively control the gate 15 via a line 17 to establish a "fast set" condition or via a line 19 to establish a "slow set" condition. The 60 Hz shaped clock pulses provided by the rate control circuit 3 are applied to the gate 15 via a line 21 and the 2 pulses per second provided by the divider 7 are applied via line 23 to the gate 15.

The output of the gate 15 is applied via a line 25 to a clock minute counter 27 and in response to an "alarm display" control signal on the line 29 via a line 31 to an alarm 10 minute counter 33. The signal on the line 25 is either the 60 Hz clock pulses in the "fast set" condition, the 2 per second pulses in the "slow set" condition or 1 pulse per minute in the normal condition. Clock minute counter 27 provides a binary count from 0 to 9 of the pulses appearing on line 25, the binary count being provided on the lines 35, 37, 39 and 41 which are connected to alarm compare circuit 43 and on lines 45, 47, 49 and 51 which are connected to a matrix switch 53, the connection between the clock minute counter 27 and matrix switch 53 for simplicity being shown as a single heavy line 55.

The clock minute counter 27 is also connected via line 57 to a clock 10 minute counter 59, the counter 27 operating in such a manner that for every ten input pulses on the line 25, a single pulse is applied to the ten minute counter 59 via the line 57.

The clock ten minute counter 59 counts the pulses appearing on line 57 to provide a binary count from 0 to 5 on lines 61, 63 and 65 which are connected to the alarm compare circuit 43 and similarly on lines 67, 69 and 71 which are connected to the matrix switch 53, the connection between the clock 10 minute counter 59 and the matrix switch 53 again for simplicity being shown as a single heavy line 73. The clock 10 minute counter 59 also provides a single pulse output via a line 75 to a clock hour counter 77 for every six pulses appearing on the line 57.

The counter 77 provides a binary count from 1 to 12 on lines 79, 81, 83 and 85 which are connected to the alarm compare circuit 43 and similarly on lines 87, 89, 91 and 93 which are connected to the matrix switch 53. The connection between the counter 77 and the matrix switch 53 is again for simplicity shown as a heavy line 95.

The pulses appearing on the line 31 of gate 15 when an "alarm display" control signal is provided on line 29 are applied to the alarm ten minute counter 33 as previously stated, the counter 33 providing a binary count from 0 to 5 for application to the alarm compare circuit 43 via the lines 97, 99 and 101 and to the matrix switch 53 via the lines 103, 105 and 107, the connection between the alarm 10 minute counter 33 and the matrix switch 53 again for simplicity being shown as a heavy line 109. A single output pulse is provided via line 111 to an alarm hour counter 113, for every six pulses appearing on the line 31.

The alarm hour counter 113 provides a binary count from 1 to 12 on the lines 115, 117, 119 and 121 which are connected to the alarm compare circuit 43 and on the lines 123, 125, 127 and 129 which are connected to the matrix switch 53. Again, the connection between the counter 113 and the matrix switch 53 is for simplicity shown as a single heavy line 131.

The alarm compare circuit provides an indication via a line 133 when the time appearing at clock counters 27, 59 and 77 becomes the same as the preset alarm time appearing at counters 33 and 113.

A strobe signal such as for example a 10 KHz signal is applied from a suitable oscillator (not shown) via a line 135 to a binary strobe counter 137 which provides a binary count from 0 to 2 on lines 139 and 141 at a 3.33 KHz rate. The lines 139 and 141 are connected to a strobe decode circuit 143 to which is also supplied via line 145 the "alarm display" control signal applied to gate 15 via line 29. In the "time display" condition in the absence of an "alarm display" control signal, the strobe decode circuit 143 produces sequential switching signals which are applied to the matrix switch 53 via the lines 147, 149 and 151. When an "alarm display" control signal is present, the strobe decode circuit 143 produces sequential switching signals which are applied to the matrix switch 53 via the lines 153 and 155.

The presence of sequential switching signals from the strobe decode circuit 143 on the lines 147, 149 and 151 in the "time display" condition sequentially switches the binary outputs of the clock minute counter 27, the clock 10 minute counter 59 and the clock hour counter 77 to a binary to decimal decoder stage 157 via the lines 159, 161, 163 and 165. Alternatively, the presence of sequential switching signals from the strobe decode circuit 143 on the lines 153 and 155 in the "alarm read" condition sequentially switches the binary outputs of the alarm ten minute counter 33 and the alarm hour counter 113 to a binary to decimal decoder stage 157.

Decimal decoder stage 157 decodes the binary information on lines 159, 161, 163 and 165 to provide decimal outputs from 0 to 12 represented by the circled numbers 0 to 12, the decimal outputs preferably being applied to a 7-bar decoding stage 167 which produces control signals on the lines 169, 171, 173, 175, 177, 179 and 181 which serve to select the appropriate bars of four parallel connected 7-bar display devices as shown in FIG. 5 to provide a digital display corresponding to a particular decimal input to the 7-bar decode stage. The binary output of the strobe counter 137 is also applied via lines 185 and 187 to the 7-bar display devices to selectively and sequentially activate the display devices in synchronism with the sequential application of tens of hours and hours, tens of minutes and minutes, outputs from the 7-bar decode 167 in parallel to the bars of the four display devices, the hours and tens of hours display devices being activated at the same time.

The operation of the circuit of the digital clock shown in FIG. 1 is such that during normal operation, a 60 Hz clock reference signal at a first voltage level of for example-9 volts is applied to line 1. At this voltage level "slow set" or "fast set" control signals are not provided on the lines 19 and 17 respectively by the rate control circuit 3 and the 1 per minute pulses on line 13 are directed by the gate 15 to the line 25 and thus to the clock minute counter 27. This produces at the input to the matrix switch 53 a binary count of hours on lines 87, 89, 91 and 93, tens of minutes of lines 67, 69 and 71 and minutes on lines 45, 47, 49 and 51, the count being advanced minute by minute in response to the pulse appearing each minute on line 25.

During normal operation the hours count, tens of minutes count and minutes counts at the input to the matrix switch 53 are sequentially switched to the output lines 159, 161, 163 and 165 of the matrix switch 53 by switching signals sequentially produced on the lines 147, 149 and 151 by the strobe decoder 143.

The output of the matrix switch 53 which is sequentially a binary count of hours, tens of minutes and minutes is applied to the decimal decoder 157 to selectively apply decimal inputs to the 7-bar decoder 167. The output of the 7-bar decoder appearing on lines 169, 171, 173, 175, 177, 179, 181 and 183 are applied in parallel to tens of hours, hours, tens of minutes and minutes 7-bar displays as shown in FIG. 5. The binary output of the strobe counter 137 appearing on lines 185 and 187 is utilized to sequentially activate the tens of hours, and the hours, tens of minutes or minutes 7-bar display devices in synchronism with the appearance of corresponding binary inputs to the 7-bar decoder 167.

Assume now that for some reason, such as inadvertent disconnection, the clock counters 27, 59 and 77 are improperly set and for example produce a binary output of 5 o'clock when it is actually 10 o'clock. In order to set the clock, a clock reference signal at a higher voltage level than that present during normal operation, such as for example -27 volts, is applied to line 1. Due to the presence of the higher voltage level, the operation of the rate control circuit 3 is such as to produce a "fast set" control signal on the line 17 which when applied to the gate 15 causes the gate 15 to direct the 60 Hz pulses on line 21 to the line 25. Thus, the clock counters 27, 59 and 77 are advanced at a 60 Hz rate and rapidly approach the proper 10 o'clock setting, the advancing count being applied to the respective display devices in the same manner as during normal operation as described above.

In order to facilitate setting of the clock as the desired 10 o'clock setting is approached at the 60 Hz rate, the 60 Hz clock reference signal applied to line 1 is decreased to a voltage level intermediate that present for normal condition and that applied for the "fast set" condition -- for example -13 volts. In response to the intermediate voltage level on line 1, the rate control circuit 3 produces a "slow set" control signal on line 19. The application of the "slow set" control signal to the gate 15 causes the gate 15 to direct the 2 per second pulses from divider 7 to the clock minute timer 27 via line 25. The clock counters 27, 59 and 77 and thus the hours, tens of minutes and minutes displays are thus advanced at the 2 pulse per second rate until the proper setting is achieved at which time the voltage on line 1 is reduced to the normal voltage level and the clock resumes normal operation.

Assume now that it is desired to set the alarm counters 33 and 113. To accomplish this an "alarm set" control signal is applied to the gate 15 via the line 29. This causes the gate 15 to direct either the 2 pulses per second on line 23 or the 60 Hz pulses on line 21 to the alarm 10 minute counter 33 via line 31 depending on the presence of either a "slow set" control signal on line 19 or a "fast set" control signal on line 17 respectively in response to the voltage level of the 60 Hz clock reference signal on line 1 in the same manner as previously discussed.

Thus, the alarm 10 minute counter 33 and alarm hour counter 113 are advanced at either a 2 per second or 60 Hz rate, the respective binary counts being applied to the input to the matrix switch 53 by the lines 123, 125, 127 and 129 and lines 103, 105 and 107. The presence of an "alarm set" signal on line 29 causes a similar signal to be applied to the strobe decoder 143 thereby causing the strobe decoder to apply a sequential switching signal to the matrix switch 53 via the lines 153 and 155 and causing the binary count of the alarm hour counter 113 and of the alarm 10 minute counter 33 to be sequentially switched to the output of the matrix switch 53 on lines 159, 161, 163 and 165. The count of the alarm counters 33 and 113 are thus displayed on the display devices in the same manner as the clock counters and is advanced, preferably at the "slow set" rate as the desired setting is approached, until the desired alarm setting is reached. At this time the "alarm set" control signal is removed from line 29 and normal clock operation continues.

An alarm indication is provided by the alarm compare circuit 43 on line 133 when the clock counters 27, 59 and 77 advance to the same count preset on the alarm counters 33 and 113. Thus, when the binary count of the clock hour counter 77 appearing on lines 79, 81, 83 and 85 is the same as that of the alarm hour counter 113 appearing on lines 115, 117, 119 and 121 and the binary output of the clock 10 minute counter 49 appearing on lines 61, 63 and 65 is the same as that of the alarm 10 minute counter 33 appearing on lines 97, 99 and 101 and the binary count of the clock minute counter 27 appearing on lines 35, 37, 39 and 41 is zero an alarm signal is provided on line 133 by the alarm compare circuit 43.

In accordance with the invention as depicted generally in FIG. 1, an electronic digital clock is provided that is easily set, small, inexpensive and accordingly ideally suited for consumer use.

Indeed, the electronic digital clock shown in FIG. 1 is particularly suited for monolithic integration and requires but a minimum number of terminals thereby decreasing cost and increasing reliability and circuit yield. More specifically the digital clock of the invention is particularly suited for integration in metal oxide semiconductor integrated circuit form utilizing but 16 terminals. Such a MOS circuit requires a minimum number of processing steps while permitting extremely small geometries and corresponding efficient use of chip area. Even further such a MOS circuit permits the use of very high effective resistances permitting the use of a large number of components having a low total power dissipation and also utilizes operating voltage levels that are compatible with presently available low cost fluorescent display tubes.

Referring now to FIG. 2, there is shown a logical diagram of the counting rate control circuit 3 of the invention, like reference numerals being utilized in FIG. 2 for those elements common to FIG. 1.

As depicted, the 60 Hz clock reference signal on line 1 is applied to an amplifier 201, which shapes the reference signal into a 60 Hz square wave signal on line 5. The clock reference signal on line 1 is also applied to a first voltage divider comprising field effect transistors FET 1, FET 2 and FET 3 serially connected between line 1 and ground. FET 1 and FET 2 have their respective drain and gate electrodes directly connected together whereas a fixed bias of for example -27 volts is applied to the gate electrode of FET 3 which has its source electrode grounded. In this manner, the first voltage divider consists of the high impedance of the constant biased FET 3 and the threshold voltage drop of FET 1 and FET 2 which function in a manner similar to reverse biased Zener diodes.

Similarly, the clock reference signal at line 1 is applied to a second voltage divider comprising field effect transistors FET 4 and FET 5 serially connected between line 1 and ground. FET 4 has its drain and gate electrodes directly connected together while FET 5 has its gate electrode connected to a fixed bias of -27 volts and its source electrode grounded, the second voltage divider thus consisting of the high impedance of the constant biased FET 5 and the threshold drop of FET 4 which again functions in a manner similar to a reverse biased Zener diode.

The signal at the junction between FET 2 and FET 3 is shaped by an amplifier 209 and is applied to the direct reset input R.sub.DF of a toggle flip flop 213 and the set input S.sub.F of a latch flip flop 215. The output Q.sub.1 of the toggle flip-flop 213 is applied to one input of a NOR gate 217 to the other input of which are applied the 60 Hz shaped pulses appearing on line 5. The 60 H.sub.z pulses are also applied to the toggle input T of flip-flop 213. The output of the NOR gate is applied to the reset input R.sub.F of the latch flip flop 215. In this manner a "fast set" control signal is developed at the output Q.sub.F of latch flip-flop 215 for application to the line 17.

Similarly, the signal at the junction between FET 4 and FET 5 of the second voltage divider is shaped by amplifier 219, the shaped signal at the output of amplifier 219 being applied to the direct reset input R.sub.DS of a toggle flip-flop 223 and to the set input S.sub.S of a latch flip-flop 225. The shaped 60 Hz pulses on line 5 are applied to the toggle input T of the toggle flip flop 223, the output Q.sub.2 of the toggle flip-flop 223 being applied to one input of a NOR gate 227 to the other input of which are applied the 60 Hz shaped pulses on line 5. The output of the NOR gate 227 is applied to the reset input R.sub.S of the latch flip-flop 225. In this manner a "slow set" control signal is developed at the output Q.sub.S of the latch flip-flop 225 and thus on line 19.

The operation of the rate control circuit of FIG. 2 is such that during normal operation a 60 Hz clock reference signal of for example -8 volts amplitude is applied to line 1.

Amplifier 201 provides a 60 Hz pulse having an amplitude for example -13 volts on the line 5.

During normal operation, with -8 volts applied between line 1 and ground across the first voltage divider the voltage drop across FET 1 and FET 2 produces a voltage of approximately 0 volts at the junction between FET 2 and FET 3, this voltage being insufficient to cause amplifier 209 to change state.

A similar condition exists for the second divider during normal operation, a voltage of approximately -3 volts being produced at the junction between FET 4 and FET 5, which is again insufficient to cause amplifier 219 to change state.

When the voltage of the 60 Hz clock reference signal on line 1 is increased to approximately -14 volts for "slow set" operation, the voltage drop across FET 4 produces a voltage of approximately -8 volts at the junction of FET 4 and FET 5 which is sufficient to cause amplifier 219 to change state.

However, during "slow set" operation, the voltage drop across FET 1 and FET 2 produces a voltage of approximately -2 volts at the junction between FET 2 and FET 3 which remains insufficient to cause amplifier 209 to change state.

When the voltage of the 60 Hz clock reference signal on line 1 is increased to approximately -27 volts for "fast set" operation, the voltage drop across FET 1 and FET 2 produces a voltage of approximately -14 volts at the junction between FET 2 and FET 3 which is then sufficient to cause amplifier 209 to change state. The voltage drop across FET 4 during "fast set" operation causes a voltage of about -20 volts to appear at the junction of FET 4 and FET 5. Thus both amplifiers 209 and 219 are caused to change state during "fast set" operation.

The detailed logical operation of the counting rate control circuit of FIG. 2 is most easily understood by reference to the waveform diagrams of FIG. 4. FIG. 4(a) depicts the clock reference signal applied to line 1 which for example during time t.sub.1 is at -8 volts to establish normal operation, during time t.sub.2 is at -27 volts to establish fast set operation, during time t.sub.3 at -14 volts to establish slow set operation and during time t.sub.4 is again at -8 volt level to re-establish normal operation.

FIG. 4(b) depicts the shaped 60 Hz pulses appearing on line 5 which as shown in FIG. 2 are applied to the trigger inputs T of the toggle flip-flops 213 and 223 and one input of each of the NOR gates 217 and 227.

FIGS. 4(c) through (f) respectively depict the wave shapes at the direct reset input R.sub.DS of toggle flip-flop 223, the Q.sub.2 output of the toggle flip-flop 223, the reset input R.sub.S of the latch flip-flop 225 as derived from the output of the NOR gate 227 and the Q.sub.S output of the latch flip-flop 225 at which appears the slow set control signal applied to line 19.

Similarly, FIGS. 4(g) through (j) respectively depict the wave shapes at the direct reset input R.sub.DF of toggle flip-flop 213, the Q.sub.1 output of the toggle flip-flop 213, the reset input R.sub.F of the latch flip-flop 215 as derived from the output of the NOR gate 217 and the Q.sub.F output of the latch flip-flop 215 at which appears the fast set control signal applied to line 17.

In the wave forms of FIG. 4(b) through (j) a logic "0" corresponds to a voltage of approximately zero volts whereas a logic "1" corresponds to a signal of approximately -13 volts.

The following truth tables describe the operation of the toggle flip-flop 213 and latch flip-flop 215 as depicted in the associated waveforms of FIG. 4. The negative and positive signs associated with the outputs of the flip-flops 213 and 215 in the truth tables indicate the existing and new output state respectively.

(1) Toggle flip flop 213 The toggle flip flop 213 R.sub.DF Q.sub. - Q.sub.1 + changes state each time 0 1 0 the trigger signal at T 0 0 1 changes from the "0" to 1 1 1 "1" state but only when 1 0 1 R.sub.DF is "0." When R.sub.DF is "1" the trigger signal at T has no effect.

(2) Latch Flip Flop 215 The state where S.sub.F and S.sub.F R.sub.F Q.sub.F - Q.sub.F + R.sub.F are both 1 is not 0 0 0 0 permitted. 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1

Similarly the following truth tables apply to the operation of the toggle flip-flop 223 and latch flip-flop 225, tables 1 and 3 being generally identical and table 4 differing from table 2 only in that for flip-flop 215 (table 2) the true output is utilized whereas for flip-flop 225 (table 4) the complementary output is utilized.

(3) Toggle Flip Flop 223 The toggle flip flop 223 R.sub.DS Q.sub.2 - Q.sub.2 + changes state each time 0 1 0 the trigger signal at T 0 0 1 changes from the "0" to 1 1 1 "1" state but only when 1 0 1 R.sub.DS is "0." When R.sub.DS is "1" the trigger signal at T has no effect.

(4) Latch Flip Flop 225 The state where S.sub.S and S.sub.S R.sub.S Q.sub.S - Q.sub.S + R.sub.DS are both "1" is not 0 0 1 1 permitted. 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 0 1 0 0 0

It will be seen from FIG. 4 and the above truth tables that for normal operation during times t.sub.1 and t.sub.4 when the clock reference signal applied to line 1 is at the -8 volt level, the logical operation of the toggle flip-flop 223, NOR gate 227 and latch flip-flop 225 is such as to produce a "1" output Q.sub.S on the line 19. However for "fast set" and "slow set" operation when the clock reference signal is at -14 and -27 volts during times t.sub.2 and t.sub.3 respectively the logical operation of these elements is such as to produce a "0" output Q.sub.S on the line 19.

Similarly for normal operation during times t.sub.1 and t.sub.4 it will be seen that the logical operation of the toggle flip-flop 213, NOR gate 217 and latch flip-flop 215 is such as to produce a "0" output Q.sub.F on the line 17. However, for "fast set" operation when the clock reference signal is at -27 volts during time t.sub.2 the logical operation of these elements is such as to produce a "1" at the output Q.sub.F on the line 17. For "slow set" operation during the time t.sub.3 the output Q.sub.F on line 17 is seen to return to the "0" state.

Thus, the logical operation of the circuit of FIG. 2 can be represented by the following table:

(5) Clock Reference Condition Signal Voltage Q.sub.S Q.sub.F __________________________________________________________________________ Normal -8V 1 0 Slow set -14V 0 0 Fast set -27V 0 1 __________________________________________________________________________

the outputs of the counting rate control circuit 3 of FIG. 2 as represented by table 5 are applied to the gating circuit 15 to cause the gating circuit to direct 1 pulse per minute to the clock minute counter during "normal" operation and either 2 pulses per second during "slow set" operation or 60 pulses per second during "fast set" operation to either the clock minute counter 27 or the alarm 10 minute counter 33 as shown in FIG. 1.

Referring now to FIG. 3 there is shown the logical diagram of the gate 15 depicted generally in FIG. 1, like reference numerals being utilized to identify those elements common to FIGS. 1 and 3.

The two per second pulses appearing on line 23 are applied to the first input of a three input NOR gate 301, to the second and third inputs of which are applied the "fast set" control signal on line 17 and the "slow set" control signal on line 19 respectively from the rate control circuit shown in FIGS. 1 and 2.

The "fast set" control signal on line 17 is also applied via an inverter 303 to one input of a NOR gate 305 to the other input of which are applied the shaped 60 Hz clock pulses on line 21. The output of NOR gate 305 is applied to one input of a two input NOR gate 307 to the other input of which is applied the output of NOR gate 301. The output of NOR gate 307 is applied to one input of a two input NOR gate 309 and also to one input of a two input NOR gate 311, the NOR gates 309 and 311 along with inverter 313 comprising a data stream switch.

The "alarm read" control signal on line 29 is applied via an inverter 313 to the second input of NOR gate 309, this signal being applied directly to the second input of the NOR gate 311. The output of the NOR gate 311 is applied to the alarm ten minute counter 33 via the line 31 as depicted in FIG. 1. The "alarm read" control signal is also applied via line 145 as depicted in FIG. 1 to the strobe decoder 143.

The output of the NOR gate 309 is applied to one input of a two input NOR gate 315 to the other input of which is applied the 1 per minute pulses appearing on line 13. The output of the NOR gate 315 is inverted by an inverter 317 and applied to the clock minute counter 27 via the line 25 as depicted in FIG. 1.

The operation of the gating circuit of FIG. 3 is such that the application of a "1" to one input of NOR gate 311 via line 29 also results in a "0" being applied to the input of NOR gate 309 due to the action of inverter 313. In this manner any pulses appearing at the output of NOR gate 307 also appear in inverted form at the output of nor gate 309 but not at the output of NOR gate 311. Conversely, the application of a "0" to line 29 results in a "0" being applied to the input of NOR gate 311 and through the action of inverter 313 a "1" being applied at the input to NOR gate 309, thereby causing any pulses appearing at the output of NOR gate 307 to also appear in inverted form at the output of NOR gate 311 for application to alarm 10 minute counter 33 via line 31 but not at the output of NOR gate 309. The NOR gates 309 and 311 and inverter 313 are thus seen to comprise a data stream switch for any pulses appearing at the output of NOR gate 307, a "1" on line 29 establishing a "clock display" condition while a "0" on line 29 establishes an "alarm display" condition.

Assuming the presence of a "1" on line 29 thereby establishing a "clock display" condition, the operation of the gating circuit of FIG. 3 is such that during normal operation when, as seen from table 5, a "0" and a "1" are applied to NOR gate 301 via lines 17 and 19 respectively by the rate control circuit 3, the output of NOR gate 301 is "0" and the 2 pulses per second applied to the input of the NOR gate 305 via line 23 do not, due to the presence of a "1" on line 17, appear at the output of the NOR gate 305. Also during normal operation the "0" appearing on line 17 is inverted by inverter 303 thus applying a "1" to one input of the NOR gate 305 such that the output of the NOR gate 305 remains "0" and the 60 Hz pulses applied to NOR gate 305 via line 21 do not appear at the output thereof.

Since the two inputs to the NOR gate 307 are accordingly "0" during normal operation, the output of that NOR gate is a "1" thereby causing the output of NOR gate 309 to be a "0". Thus, the 1 pulse per minute applied to a NOR gate 315 via line 13 appears in inverted form at the output thereof and is again inverted by inverter 317 and applied via line 25 to clock minute counter 27.

During "slow set" operation as seen from table 5, the input to NOR gate 301 on line 17 becomes "0" thereby causing the 2 pulses per second applied to NOR gate 301 via line 23 to appear in inverted form at the output thereof.

Since the 60 Hz pulses still do not appear at the output of NOR gate 305 in this condition, the two pulses per second at the output of NOR gate 301 are twice inverted by NOR gates 307 and 309 and applied to an input of NOR gate 315. Since the other input to NOR gate 315 is "0" for all but the pulse interval of the 1 pulse per minute applied to line 13, which is short compared to the 2 pulses per second appearing at the output of NOR gate 309, the latter pulses are accordingly inverted by NOR gate 315 and again by inverter 317 and applied via line 25 to clock minute counter 27.

During "fast set" operation the input to NOR gate 301 appearing on line 17 becomes "1" as seen from table 5 such that the 2 pulses per second no longer appear at the output of NOR gate 315. However, due to the action of inverter 303 a "0" now appears at the input to NOR gate 305 and 60 pulses per second appear in inverted form at the output of NOR gate 305, this output being twice inverted by NOR gates 307 and 309 and applied to NOR gate 315. Again since the other input to NOR gate 315 is "0" for all but the pulse interval of the 1 pulse per minute applied to line 13, which is short compared to the 60 pulses per second appearing at the output of NOR gate 309, the latter pulses are accordingly inverted by NOR gate 315 and again by inverter 317 and applied via line 25 to clock minute counter 27.

Now assuming the presence of a "0" on line 29 thereby establishing an "alarm display" condition, the logical operation of the gating circuit of FIG. 3 is generally the same as described above except that in the "fast set" condition the 60 Hz pulses at the output of NOR gate 307 are directed through NOR gate 311 to the alarm ten minute counter 33 via line 31 while in the "slow set" condition the 2 pulses per second at the output of NOR gate 307 are similarly directed.

It will thus be seen that 1 pulse per minute is applied to the clock minute counter 27 via line 25 both during the normal condition and also when the level of the clock reference signal on line 1 is such as to establish the "fast set" or "slow set" condition and a logical "0" is applied to line 29 thereby establishing an "alarm set" condition. However, when a "clock set" condition is established by the application of a "1" to line 29 either 60 pulses per second or 2 pulses per second depending on the level of the clock reference signal on line 1 are applied to the clock minute counter 27 via line 25. Thus, the alarm counters 33 and 113 will retain their preset count at all times unless a "0" is applied to line 29 and at the same time either a "0" is applied to line 19 to "slow set" the alarm or a "1" is applied to line 17 to "fast set" the alarm.

Referring now to FIG. 5, there is shown a preferred form of input-output circuit for use with the electronic digital clock of FIG. 1.

As depicted, a transformer T1 is provided across the primary 501 of which is applied the 120 V AC line voltage, transformer T1 including secondary windings 503, 505, 507 and 509.

The secondary 503 applies power to the filament of a conventional seven bar display tube V1 while secondary 505 applies power to the filament of a second seven bar display tube V2 whereas filament 507 applies power in parallel to the filaments of third and fourth seven bar display tubes V3 and V4.

The seven bar display tubes V1, V2, V3 and V4 provide a display of minutes, tens of minutes, hours and tens of hours respectively.

As depicted, the outputs of the seven bar decoder shown in FIG. 1 are applied in parallel via the lines 171, 173, 175, 177, 179, 181 and 183 to corresponding electrodes of tubes V1, V2 and V3. Since tube V4 provides a tens of hours display and accordingly is at no time required to display more than a "1" the output of the seven bar decoder is applied via line 169 to a pair of electrodes of tube V4 which provide a numeral 1 display.

A voltage regulator is connected across secondary 509 of transformer T1, the voltage regulator comprising transistors TR1, TR2, diode D1, Zener diode D2, capacitor C1 and resistors R1, R2 and R3. The voltage regulator serves to provide a regulated DC voltage of -27 volts between line 511 and ground and -13 volts between ground and the junction of transistor TR2 and Zener diode D2 as shown. The -27 and -13 volt supplies thus provided are utilized to energize the electronic digital clock shown in FIG. 1.

A voltage level selection circuit for the clock reference signal applied to line 1 of FIG. 1 is also provided. The voltage level selection circuit comprises a resistor R4 and capacitor C2 serially connected across the secondary 509 and the serial combination of resistors R5, R6, R7 and the emitter collector circuit of transistor TR3 connected between ground and line 511. The base of transistor TR3 is connected via a resistor R8 to the junction between resistor R4 and capacitor C2. A double pole single throw switch S1 including terminals 515, 517, 519, 521, 523 and 525 and a single pole-single throw switch S2 including terminals 527, 529 and 531 are provided to permit selection of the particular clock reference signal voltage level necessary to establish "normal," "slow set" or "fast set" operation, the switches being shown in their "normal" positions. The junction between resistors R5 and R6 is connected to terminal 517 of switch S1 while the junction between resistors R6 and R7 is connected to terminal 527 of switch S2 whereas the junction between resistor R7 and transistor TR3 is connected to terminal 523 of switch S1.

The operation of the voltage level selection circuit of FIG. 5 is such that the application of the 60 Hz sine wave appearing across secondary 509 to the base of TR 3 develops a 60 Hz square wave varying between 0 and -27V across the voltage divider comprising R5, R6 and R7, the resistor R4 and capacitor C2 serving to prevent the application of noise impulses appearing across secondary 509 to the base of transistor TR3.

Thus with switches S1 and S2 in the "normal" position as shown, a square wave having an amplitude of approximately -8 volts at the junction of resistors R5 and R6 is applied via terminals 517, 519, 531 and 529 to line 1.

With switch S1 in the "fast set" position, a square wave having an amplitude of -14 volts at the junction of transistor TR3 and resistor R7 is applied via terminals 523 and 521 to line 1.

With switch S2 in the "slow set" position, a square wave having an amplitude of -14 volts at the junction of resistors R6 and R7 is applied via terminals 527 and 529 to line 1.

A display tube switching circuit is also provided comprising switching transistors TR4, TR5 and TR6. The emitters of transistors TR4, TR5 and TR6 are connected to line 511 and thus to -27 volts whereas the collectors are respectively connected through resistors R9, R10 and R11 to ground. The collector of transistor TR4 is also connected to the parallel connected filaments of display tubes V3 and V4 whereas the collectors of transistors TR5 and TR6 are respectively connected to the filaments of display tubes V2 and V3. The base of each transistor is connected to line 511 and thus to -27 volts via resistors R12, R13 and R14 respectively.

The binary output of strobe counter 137 as shown in FIG. 1 is applied via line 185 and resistor R15 to the base of transistor TR4 and via line 187 and resistor R16 to the base of transistor TR5, the collector electrodes of transistors TR4 and TR5 being connected to the base electrode of transistor TR6 through diodes D3 and D4 respectively.

The operation of the display tube switching circuit of FIG. 5 is such that the application of a binary count from 1 to 3 on lines 185 and 187 by the strobe counter 137 as shown in FIG. 1 renders the transistors TR4, TR5 and TR6 conductive in sequential fashion in accordance with the following table:

(6) Line 185 Line 187 TR4 TR5 TR6 __________________________________________________________________________ 0 1 ON OFF OFF 1 0 OFF ON OFF 1 1 OFF OFF ON __________________________________________________________________________

as transistors TR4, TR5 and TR6 are sequentially rendered conductive, the voltage at the collector of each transistor in turn approaches -27 volts. Thus when transistor TR4 is conductive -27 volts is applied to the parallel connected filaments of display tubes V3 and V4 thereby enabling those tubes. Similarly when transistor TR5 is conductive display tube V2 is enabled whereas when transistor TR6 is conductive display tube V1 is enabled.

In this manner, the minutes display tube V1, tens of minutes display tube V2 and hours display tubes V3 and V4 are sequentially enabled in synchronism with the sequential application of minutes, tens of minutes and hours counts to the appropriate electrodes of the display tubes by the 7 bar decoder via lines 169, 171, 173, 175, 177, 179, 181 and 183.

Although the invention has been described with respect to certain specific embodiments, it will be appreciated that modifications and changes may be made by those skilled in the art without departing from the true spirit and scope of the invention.

* * * * *

Current U.S. Class:	368/87 ; 368/187; 368/200; 968/891; 968/910; 968/961; 968/972
Current International Class:	G04G 13/00 (20060101); G04G 13/02 (20060101); G04G 9/00 (20060101); G04G 19/06 (20060101); G04G 9/10 (20060101); G04G 5/00 (20060101); G04G 19/00 (20060101); G04G 5/02 (20060101); G04c 003/00 (); G04c 021/04 (); G04b 019/30 ()
Field of Search:	58/23,50,38,23A