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United States Patent | 3,568,152 |
Jallen | March 2, 1971 |
Arrangement for preconditioning a memory system having selectable address lines to reduce adverse effects arising during addressing caused by the effective shunt capacitance of the memory. The effective shunt impedance of the memory system is increased by a switching arrangement which permits the stray capacitances of the system to be charged prior to completion of a current path through a selected address line. When such a current path is subsequently completed, the switching arrangement bypasses enough current from this path to prevent the memory from being actuated. However, during this period the effective shunt capacitance associated with the selected path discharges. Thus, when the bypass is subsequently interrupted, full current passes through the selected address line without encountering adverse effects caused by shunt capacitance.
Inventors: | Jallen; Gale A. (Roseville, MN) |
Assignee: |
Control Data Corporation
(Minneapolis,
MN)
|
Appl. No.: | 04/681,508 |
Filed: | November 8, 1967 |
3027546 | March 1962 | Howes et al. |
3192510 | June 1965 | Flaherty |
3210741 | October 1965 | Cohler et al. |
3293626 | December 1966 | Thome |
3319233 | May 1967 | Amemiya et al. |
3343147 | September 1967 | Ashwell |
"Array Charging Technique" by J. A. Lake Jr., IBM Tech. Disc. Bull., Vol. 8, No. 4, Sept. 1965, P. 597 . "Memory Drive System" by Caricari & Fugere IBM Technical Disclosure Bulletin Vol. 9 No. 7 Dec. 1966 pgs. 928--929. |